Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!ncar!oddjob!mimsy!chris From: chris@mimsy.UUCP (Chris Torek) Newsgroups: comp.arch Subject: Re: SPARC and multiprocessing Message-ID: <11389@mimsy.UUCP> Date: 7 May 88 07:53:03 GMT References: <22227@pyramid.pyramid.com> Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742 Lines: 12 [Virtual caches vs bus snooping with physical addresses] Another possibility---if perhaps somewhat unusual and maybe quite difficult---would be to be able to spot invalid cache accesses and fault the original instruction before it is allowed to complete. That is, allow the instruction to execute using the cached data, and if the cached data is stale, zap it before it is too late. I imagine this would get nightmarish when debugging the hardware. -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163) Domain: chris@mimsy.umd.edu Path: uunet!mimsy!chris