Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!purdue!decwrl!nsc!voder!apple!bcase From: bcase@Apple.COM (Brian Case) Newsgroups: comp.arch Subject: Re: RISC a short answer?? Message-ID: <9341@apple.Apple.Com> Date: 6 May 88 17:37:31 GMT References: <1036@nusdhub.UUCP> <1988May3.224604.2252@utzoo.uucp> <383@m3.mfci.UUCP> <1988May5.171444.849@utzoo.uucp> Reply-To: bcase@apple.UUCP (Brian Case) Organization: Apple Computer Inc, Cupertino, CA Lines: 45 In article <1988May5.171444.849@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes: >Yes, it is true that optimizing compilers are a crucial part of many "RISC" >projects today. It is also true that RISC architectures tend to be good >for optimization, since they give the compiler more control (and distract >it less with complex side issues). This is a useful side effect of RISC >designs, which makes them more popular. It is not a fundamental part of >the RISC concept. I disagree completely. I think the whole point of RISC is to properly match hardware with the capabilities of software (particularly the software that generates the code that determines the state transitions, i.e. the compiler). Before RISC was called RISC, John Cocke was inventing it. His motivation was the needs of optimizing compilers. >Reduced Instruction Set means fewer and less complex instructions. That >is all it means. Wow, I didn't think I'd ever see this comment. I believe that you'd have a hard time finding anybody who has designed or is designing a RISC machine, and I realize it is hard to define this term for my purposes here, who would define RISC the way you did. I plan on posting a summary of RISC-related literature ("The story of RISC :-), starting with the earliest papers by Patterson and Ditzel (incl. "The Case for the Reduced Instruction Set Computer." Has anyone who is arguing these issues actually read all the relavent literature???), but let me now give my personal, back-of- the-business-card summary of RISC: 1) Uniform Pipeline (all, or nearly all, instructions flow through the pipeline in the same way) 2) Good match to optimizing compiler technology (the architecture makes it easy for the compiler in several ways: code generation, code motion, register allocation, etc., and *calculating the cost of code sequences* in both time and space) 3) Allows technology to be exploited (cycle time dominated by some "irreducible" component of computation like an ALU or Cache lookup; yes, I know you can pipeline ALUs and cache lookups, but do you really want to?) Notice that there will be implementations of CISC machines that have these characteristics to pretty high degrees! The junky instructions/addressing modes will be done "off line" while the things that: fit in a uniform pipe, are needed by compilers, and allow a fast cycle time will be done in hardware. There is a big cost, but it can and will be done. RISC is a way of doing things, not a thing.