Path: utzoo!mnetor!uunet!husc6!bbn!gatech!udel!rminnich From: rminnich@udel.EDU (Ron Minnich) Newsgroups: comp.arch Subject: Re: Is the Intel memory model safe from NO-ONE ?!? Message-ID: <2429@louie.udel.EDU> Date: 8 May 88 16:50:07 GMT References: <1806@obiwan.mips.COM> <2904@omepd> <353@cf-cm.UUCP> <22830abd:a11@snark.UUCP> Reply-To: rminnich@udel.EDU (Ron Minnich) Organization: University of Delaware Lines: 24 In article <22830abd:a11@snark.UUCP> eric@snark.UUCP (Eric S. Raymond) writes: > Segmented architecture -- one in which the register width is not > sufficient to address all of memory, so that full addresses must > be base/offset or segment-descriptor/address pairs. Nope. Wrong. Take a look at the Burroughs architecture of the early sixties, withe their 20 bit address, and tell me that people built machines with 6 Mb of memory around then (the 20-bit address was for 48-bit words). Your definition demonstrates my thesis- that people think of Intel when they think of segments, and they think that segments are a way of getting around small addressing models. Intel did it wrong. > Memory protection -- the ability to enforce memory addressing restrictions > on execution threads so that references outside a 'legal' region are > detected and trapped (in UNIX terms, raise a SIGSEGV). In any real program, there are a large number of legal regions, which you don't want to get confused. Flat address space machines do not help in this regard. At most they provide two regions (code and data). The NULL pointer joke was an aside. What you really want is to (e.g.) keep array references from going to the wrong place, and that is what segments help enforce. In a flat address space, two arrays of structures butted against each other can (and do!) become confused; in a segmented machine done right, they can't; in most Intel machines, they can (and do!) become confused (in the tiny, small, medium, and large models, for example). -- ron (rminnich@udel.edu)