Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!ll-xn!mit-eddie!uw-beaver!cornell!rochester!pt.cs.cmu.edu!andrew.cmu.edu!jk3k+ From: jk3k+@andrew.cmu.edu (Joe Keane) Newsgroups: comp.arch Subject: Re: RISC vs CISC on Low-End Processors Message-ID:Date: 11 May 88 21:44:57 GMT References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <9561@sol.ARPA>, <1658@pt.cs.cmu.edu> Organization: Carnegie Mellon Lines: 14 In-Reply-To: <1658@pt.cs.cmu.edu> > How about stack architectures? They seem to meet the criteria you set forth. > Does anyone have arguments for or against them? I like them. They tend to have very compact code (and more decoding), not the trend these days. A neat thing is that you can make the size of the register file transparent. Want to speed up the machine, add another 64 registers. I swear half the operands in VAX code are byte offset off frame pointer (although GCC gets more into registers). On a different note, how about the Fairchild Clipper? Looks like about the right compromise (for a high-end machine). My biggest complaint is that they don't have delayed branches `because it makes it hard on the compiler'. The current implementation should be able use at least one. --Joe