Path: utzoo!mnetor!uunet!husc6!bbn!rochester!crowl From: crowl@cs.rochester.edu (Lawrence Crowl) Newsgroups: comp.arch Subject: RISC vs CISC on Low-End Processors Message-ID: <9561@sol.ARPA> Date: 10 May 88 15:43:19 GMT References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <833@imagine.PAWL.RPI.EDU> <3444@omepd> <492@pcrat.UUCP> Reply-To: crowl@cs.rochester.edu (Lawrence Crowl) Organization: U of Rochester, CS Dept, Rochester, NY Lines: 52 Keywords: RISC, real-time In article <492@pcrat.UUCP> rick@pcrat.UUCP (Rick Richardson) writes: >Widgets in plastic boxes don't pass FCC at high clock rates without a lot of >layout headaches and extraneous R's and C's. Keep the clock down around 4 >Mhz! The bus width is a big deal. We're talking parts count here. Ideally: >1 CPU, 1 RAM, 1 ROM, 1 Glue, and peripheral chips. The 16 bit bus gets the >nod only because RAM/ROM requirements exceed current state of the art in >RAM/ROM chips. Go beyond 128K ROM and you're talking two chips. Go beyond >32K (static) RAM and you're also talking two chips. I'm looking at a bunch of >consumer type applications that have outgrown the 8088 level of CPU >performance, and are moving into the 64K to 128K bytes range of RAM, and the >256K to 512K bytes range of ROM. Let me point out the differences between on low-end processors outlined above and the typical RISC processors. 1) The clock rate is limited. This means that instruction execution rate is also limited. 2) The memory bandwidth is limited. This is a consequence of a low clock, a a narrow bus, cheap memory, and no external caches. 3) Program space is limited. Programmers will always be asked to cram as much function as possible in minimal hardware. 4) Data space is limited. 5) The processor chip area is limited. Processor cost is related to area, so cheaper processor have smaller areas. Point 1 argues for maximum work per clock cycle. Both CISC and stack architectures provide noticably lower work per clock cycle than RISC architectures. Points 2 and 3 argue for a densely coded instruction set. This reduces both the memory bandwidth required to execute the program and the space required to store it. Both CISC and stack architectures generally provide dense instruction sets, RISC processors generally do not. Points 2 and 4 indicates that the processor should support variables of multiple sizes ranging, perhaps even bit fields. This is more an attribute of CISC architectures than RISC. Point 5 indicates that complex or area consuming features should be avoided. RISC and stack architectures typically require much less area than CISC. Here we have a conflict, point 2 argues for internal caches, but point 5 argues against them. These points taken together seem to indicate that we want neither RISC nor CISC, but the appropriate compromise. The CRISP processor appears to have addressed this compromise well. I do not know enough about the architecture to say whether or not it meets the requirements, but it appears much closer than many other architectures. -- Lawrence Crowl 716-275-9499 University of Rochester crowl@cs.rochester.edu Computer Science Department ...!{allegra,decvax,rutgers}!rochester!crowl Rochester, New York, 14627