Path: utzoo!mnetor!uunet!husc6!tut.cis.ohio-state.edu!cypress.cis.ohio-state.edu!mills-c
From: mills-c@cypress.cis.ohio-state.edu (Christopher Mills)
Newsgroups: comp.arch
Subject: Re: Do RISC Compilers Consider Multiprogramming?
Message-ID: <12778@tut.cis.ohio-state.edu>
Date: 9 May 88 16:54:02 GMT
References: <620@speedy.mcnc.org> <10707@steinmetz.ge.com>
Sender: news@tut.cis.ohio-state.edu
Organization: The Ohio State University Dept of Electrical Engineering
Lines: 30
Keywords: RISC compiler context-switch architecture multiprogramming

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In article <10707@steinmetz.ge.com> davidsen@crdos1.UUCP (bill davidsen) writes:
>   
>  Interesting thought from the past... the GE 600 series allowed
>interrupts on an instruction fetch from an even location (since the bus
>was 72 bits wide that was every other instruction). This resulted in the
>ability to preserve context throught a few instructions.
>
>  What are the ramification of doing the same thing on a newer
>processor?

>	bill davidsen		(wedu@ge-crd.arpa)


	Hmm.  Doesn't the Transputer already do this?  Context switches (for
low priority tasks) are permitted only after unconditional jumps, loops, and
instructions that can cause the task to block (I/O).  The state of the
evaluation registers are undefined after these instructions, so the context
switch consists of only the PC and the Workspace Pointer.  The compiler doesn't
usually care about the evaluation registers during a branch, and there is
always a chance for a context switch each time through a loop.  I think it's a
good solution, concidering the goals of the Transputer, but then again, what
do I know?


				Chris Mills
				mills@baloo.eng.ohio-state.edu

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