Path: utzoo!attcan!uunet!husc6!bbn!rochester!crowl From: crowl@cs.rochester.edu (Lawrence Crowl) Newsgroups: comp.arch Subject: Re: RISC vs CISC on Low-End Processors Keywords: RISC, real-time Message-ID: <9631@sol.ARPA> Date: 12 May 88 13:32:26 GMT References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <9561@sol.ARPA> <1658@pt.cs.cmu.edu> Reply-To: crowl@cs.rochester.edu (Lawrence Crowl) Organization: U of Rochester, CS Dept, Rochester, NY Lines: 16 In article <1658@pt.cs.cmu.edu> koopman@a.gp.cs.cmu.edu (Philip Koopman) writes: )In article <9561@sol.ARPA>, crowl@cs.rochester.edu (Lawrence Crowl) writes: )>... These points taken together seem to indicate that we want neither RISC )>nor CISC, but the appropriate compromise. The CRISP processor appears to )>have addressed this compromise well. ... ) )How about stack architectures? They seem to meet the criteria you )set forth. Does anyone have arguments for or against them? Stack architectures fail to meet the criteria on one point. They have a high instruction execution rate. The criteria required a low clock rate, which does not support a high instruction rate. -- Lawrence Crowl 716-275-9499 University of Rochester crowl@cs.rochester.edu Computer Science Department ...!{allegra,decvax,rutgers}!rochester!crowl Rochester, New York, 14627