Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!livesey From: livesey@sun.uucp (Jon Livesey) Newsgroups: comp.arch Subject: Re: RISC a short answer?? Message-ID: <52338@sun.uucp> Date: 6 May 88 21:46:54 GMT References: <1036@nusdhub.UUCP> <21149@pyramid.pyramid.com> <307@mucmot.UUCP> <310@mucmot.UUCP> Organization: Sun Microsystems, Inc. - Mtn View, CA Lines: 60 In article <310@mucmot.UUCP>, ron@mucmot.UUCP (Ron Voss) writes: > From article <381@m3.mfci.UUCP>, by root@mfci.UUCP (SuperUser): > > In article <307@mucmot.UUCP> ron@mucmot.UUCP (Ron Voss) writes: > > =From article <21149@pyramid.pyramid.com=, by csg@pyramid.pyramid.com > > =(Carl S. Gutekunst): > > == In article <1036@nusdhub.UUCP= rwhite@nusdhub.UUCP (Robert C. White Jr.) > > == writes: > > ===Can someone give me [short answer style] a description of what "RISC" > > ===means. > > ........... I offer an even shorter answer to Robert's (not Bob's) original > question: > 1. Instructions all the same length. > 2. Instructions execute in one cycle. > 3. Instructions are not microcoded. > (adapted from Motorola's 88000 press release) > ------------------------------------------------------------ > Ron Voss Motorola Microsystems Europe, Munich > mcvax!unido!mucmot!ron CIS 73647,752 > my opinions are just that, and not necessarily my employer's > ------------------------------------------------------------ Gee, a Motorola person offers us a definition of RISC processors in general, by quoting from a Motorola press release. O tempora, o mores. :-) Maybe you would tell me what's wrong with Tabak's [1] 1987 definition which I quoted a week ago? 1. Few instructions (< 100 is best) 2. Few addressing modes (1 or 2) 3. Few instruction formats. 4. Single cycle execution. 5. Memory access by load/store instruction only. 6. Large register set. 7. Hardwired control unit. 8. HLL support reflected in architecture Or how about Stallings' definition in [2] "The key elements shared by all of these designs are these: - A limited and simple instruction set. - A large number o general purpose registers. - An emphasis on optimizing the instruction pipeline. Note in particular, that Stallings' definition is as short as yours, but manages to characterize more of the system architecture. Maybe the question I am asking is this: if all this work has been done before, by independent people, do we really need each manufacturer to torque the definition around to suit their own product? Fine for a Press Release, but not for general purposes. jon. [I don't speak for Sun] [1] Tabak D. "RISC Architecture", Research Studies Press, 1987. [2] Stallings W. "Reduced Instruction Set Computers." IEEE Computer Society 1988.