Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!necntc!encore!bartlett
From: bartlett@encore.UUCP (John Bartlett)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing
Message-ID: <3032@encore.UUCP>
Date: 11 May 88 02:32:22 GMT
References: <51321@sun.uucp> <63900014@convex>
Reply-To: bartlett@encore.UUCP (John Bartlett)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 27

In article <63900014@convex> gruger@convex.UUCP writes:
>
>>/* Written  5:51 pm  May  2, 1988 by jeff@alliant.Sun.Com
>>	...  It is a much more
>>	complicated procedure to "watch" these addresses.  With a virtual
>
>Nah, it ain't that hard.  One can have a virtually mapped, physically tagged
>cache.  As the virtual cache is filled with data, the translated physical
>address from the MMU is written into the tag RAMs.  The physical tags are 
>then used by the bus watcher to selectively invalidate the cache entries.


This sounds easy, but every time I have anaylzed this I have come to the 
conclusion that one of those tag stores has to be fully associative, to insure
that the two tag stores will always have the same addresses allocated.  Am I
missing something here?  

In our systems, we can't afford the realestate for a fully associative tag store
for each processor cache.


John Bartlett		{ihnp4,decvax,allegra,linus}!encore!bartlett
Encore Computer Corp.
257 Ceder Hill Street
Marlboro, Mass.  01752
(617) 460-0500

Opinions are not necessarily those of Encore Computer Corp.