Path: utzoo!mnetor!uunet!mfci!root From: root@mfci.UUCP (SuperUser) Newsgroups: comp.arch Subject: Re: RISC a short answer?? Message-ID: <391@m3.mfci.UUCP> Date: 9 May 88 11:47:14 GMT References: <1036@nusdhub.UUCP= <21149@pyramid.pyramid.com= <307@mucmot.UUCP= <310@mucmot.UUCP= <52338@sun.uucp= Reply-To: mfci!colwell@uunet.UUCP (Robert Colwell) Organization: Multiflow Computer Inc., Branford Ct. 06405 Lines: 68 In article <52338@sun.uucp= livesey@sun.uucp (Jon Livesey) writes: =In article <310@mucmot.UUCP=, ron@mucmot.UUCP (Ron Voss) writes: == From article <381@m3.mfci.UUCP=, by root@mfci.UUCP (SuperUser): == = In article <307@mucmot.UUCP= ron@mucmot.UUCP (Ron Voss) writes: == = =From article <21149@pyramid.pyramid.com=, by csg@pyramid.pyramid.com == = =(Carl S. Gutekunst): == = == In article <1036@nusdhub.UUCP= rwhite@nusdhub.UUCP (Robert C. White Jr.) == = == writes: == = ===Can someone give me [short answer style] a description of what "RISC" == = ===means. = Maybe you would tell me what's wrong with Tabak's [1] 1987 definition =which I quoted a week ago? = = 1. Few instructions (< 100 is best) = 2. Few addressing modes (1 or 2) = 3. Few instruction formats. = 4. Single cycle execution. = 5. Memory access by load/store instruction only. = 6. Large register set. = 7. Hardwired control unit. = 8. HLL support reflected in architecture = = Or how about Stallings' definition in [2] = = "The key elements shared by all of these designs are these: = = - A limited and simple instruction set. = - A large number o general purpose registers. = - An emphasis on optimizing the instruction pipeline. = = Note in particular, that Stallings' definition is as short as yours, but =manages to characterize more of the system architecture. = =jon. =[1] Tabak D. "RISC Architecture", Research Studies Press, 1987. =[2] Stallings W. "Reduced Instruction Set Computers." IEEE Computer Society 1988. In Tabak's list, number 6 is wrong, and number 8 is meaningless. The number of registers in a machine has nothing to do with its RISC or CISC-ness. I think the reason everybody seems to get this confused is because the most famous RISC (RISC-I) had lots of registers and the Berkeley people did not go out of their way to point out that that style of register organization did not go hand-in-hand with RISC. Perhaps they thought that point was obvious; after all, Stanford's MIPS and the 801 did not have lots of registers. And if Tabak is merely offering the observation that many machines designed since 1981 have more registers than the VAX, then fine, but that doesn't qualify the number of registers as being a RISC litmus test. Number 8 is meaningless because "HLL support" was the holy grail that led all the CISC designs down the microcoded path, and if I can't use the list's items to help distinguish RISC from CISC, it is useless. Stalling's definition is too simple. The register issue is junked as above. The "limited and simple" item is fine. But the third can just as easily describe the extensive instruction stream lookahead/cycle-stealing techniques that characterize some CISC micros. If you remove the two items I contend are wrong in Tabak's list, it collapses to the list we published two years earlier than his (in IEEE Computer Sept. 1985, in 32-bit Microprocessors, H.J. Mitchell, Collins, 1986, and reprinted in Stalling's RISC tutorial.) Bob Colwell mfci!colwell@uunet.uucp Multiflow Computer 175 N. Main St. Branford, CT 06405 203-488-6090