Xref: utzoo comp.arch:4707 comp.parallel:49 Path: utzoo!mnetor!uunet!husc6!ukma!gatech!hubcap!SuperUser From: mfci!root@uunet.uu.net (SuperUser) Newsgroups: comp.arch,comp.parallel Subject: Re: Instruction scheduling on a VLIW machine Message-ID: <1584@hubcap.UUCP> Date: 9 May 88 12:19:03 GMT Sender: fpst@hubcap.UUCP Lines: 23 Approved: parallel@hubcap.clemson.edu In article <1549@hubcap.UUCP> ogcvax!pase@uunet.uu.net (Douglas M. Pase) writes: >Is micro-instruction scheduling considered a ``difficult'' problem on VLIW >machines? If so, why? Could you please supply some references which would >explain the problems in detail? (Try to use refs which are commonly available, >e.g. IEEE, ACM, Theo. Comp. Sci., LNCS, etc.) >-- >Doug Pase -- ...ucbvax!tektronix!ogcvax!pase or pase@cse.ogc.edu (CSNet) It's not completely clear to me what you would like to know: compacting micro-instructions into a program, trace scheduling a program, writing assembler code for a VLIW, or what is the hardest part in writing a VLIW compiler ? We have not really written up anything about our VLIW compiler per se, but the following reference might get you started: (there is a revised version of this paper forthcoming in IEEE Transactions on Computers in August.) R. Colwell, et. al., A VLIW architecture for a Trace Scheduling Compiler, 2nd Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, ACM Sigplan Notices 22:10, October 1987, pp. 193-198. Stefan M. Freudenberger, Multiflow Computer, Inc., freudenberger@multiflow.com