Path: utzoo!attcan!uunet!portal!cup.portal.com!Paul_L_Schauble
From: Paul_L_Schauble@cup.portal.com
Newsgroups: comp.arch
Subject: Re: negative addresses
Message-ID: <5355@cup.portal.com>
Date: 12 May 88 06:14:09 GMT
References: <2393@uvacs.CS.VIRGINIA.EDU>
Organization: The Portal System (TM)
Lines: 23
XPortal-User-Id: 1.1001.3295

I routinely work on a machine that almost does this, the Honeywell-Bull
GCOS mainframes. Virtual addresses are constructed from three pieces

   Descriptor       34 bits of address
   Address register 34 bit signed offset
   Index register   34 bit signed offset
   Instruction      16 bit signed offset

Oops, I meant 4 pieces. This all works fine except for one idiody committed
by the hardware designers: the machine word is 36 bits. If you do an
'effective address to register' instruction that results in a negative
address does NOT result in a negative value in the register.

This machine does not consider the 34 bit final addresses to be signed. If I
were designing the machine again, I'd make all of the internal address
calculations be 36 bits, ending with a 36 bit negative value. The, just throw
away the negative half of the address space by making those addresses fault.
If you don't think losing the address space is reasonable (and on a machine
with a small 32 bit address space you might well not), then HB could just
make the virtual addresses run -X to +X and just adjust the base addresses
in the descriptors. Very very few slave processes would ever notice.

    Paul