Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!necntc!encore!bartlett
From: bartlett@encore.UUCP (John Bartlett)
Newsgroups: comp.arch
Subject: Re: virtual cache coherency
Message-ID: <3033@encore.UUCP>
Date: 11 May 88 02:51:14 GMT
References: <1605@pt.cs.cmu.edu> <28200142@urbsdc>
Reply-To: bartlett@encore.UUCP (John Bartlett)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 28


>Which brings up the question, why don't we do IO with virtual addresses? 
>We have living proof that it can be done. Why isn't it catching on?
>
>	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science

I have considered this from time to time.  For specifically allocated channels,
like disk DMA channels, it may make sense.  For a device that can potentially
support concurrent traffic for more than one process, you need an MMU for
each thread of control, and suddenly you have an allocation problem.

The other thing that consistently gets in the way is that IO has this tendency
to require deterministic delays so various buffers don't overrun and the like.
MMUs dont lend themselves well to that.

IO also doesn't know what to do with a fault.  

All in all, considering that I/O set up time does not seem to dominate our
processors, we have chosen to continue to let the O.S. remap stuff into the
appropriate physical addresses.


John Bartlett		{ihnp4,decvax,allegra,linus}!encore!bartlett
Encore Computer Corp.
257 Ceder Hill Street
Marlboro, Mass.  01752
(617) 460-0500

Opinions are not necessarily those of Encore Computer Corp.