Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!bbn!rochester!pt.cs.cmu.edu!a.gp.cs.cmu.edu!koopman From: koopman@a.gp.cs.cmu.edu (Philip Koopman) Newsgroups: comp.arch Subject: Re: RISC vs CISC on Low-End Processors Summary: How about stack machines? Keywords: RISC, real-time Message-ID: <1658@pt.cs.cmu.edu> Date: 11 May 88 16:33:30 GMT References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <9561@sol.ARPA> Sender: netnews@pt.cs.cmu.edu Organization: Carnegie-Mellon University, CS/RI Lines: 20 In article <9561@sol.ARPA>, crowl@cs.rochester.edu (Lawrence Crowl) writes: > ... > These points taken together seem to indicate that we want neither RISC nor > CISC, but the appropriate compromise. The CRISP processor appears to have > addressed this compromise well. I do not know enough about the architecture > to say whether or not it meets the requirements, but it appears much closer > than many other architectures. How about stack architectures? They seem to meet the criteria you set forth. Does anyone have arguments for or against them? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ Phil Koopman 5551 Beacon St. ~ ~ Pittsburgh, PA 15217 ~ ~ koopman@faraday.ece.cmu.edu (preferred address) ~ ~ koopman@a.gp.cs.cmu.edu ~ ~ ~ ~ Disclaimer: I'm a PhD student at CMU, and I do some ~ ~ work for WISC Technologies. ~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~