Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ll-xn!mit-eddie!bloom-beacon!mcgill-vision!mouse From: mouse@mcgill-vision.UUCP (der Mouse) Newsgroups: comp.arch Subject: Re: 80960 IO Message-ID: <1086@mcgill-vision.UUCP> Date: 9 May 88 22:07:51 GMT References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <253@babbage.acc.virginia.edu> Organization: McGill University, Montreal Lines: 17 In article <253@babbage.acc.virginia.edu>, mac3n@babbage.acc.virginia.edu (Alex Colvin) writes: >> Caching is not the only problem with I/O devices. It is (was?) >> common practice for status registers to be cleared upon being read. > All too common a practice! Stop it! If I'd 'a wanted it cleared I'd > 'a done a read-and-clear! How many machines *have* a read-and-clear instruction? (No, the read-and-clear must be atomic, you're not allowed to use two instructions to do it.) > Would you do this to a processor register? Ever hear of the PDP-8? der Mouse uucp: mouse@mcgill-vision.uucp arpa: mouse@larry.mcrcim.mcgill.edu