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From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: Horizontal Pipelining -- a pair
Message-ID: <28200073@ccvaxa>
Date: Fri, 27-Nov-87 16:11:00 EST
Article-I.D.: ccvaxa.28200073
Posted: Fri Nov 27 16:11:00 1987
Date-Received: Mon, 30-Nov-87 02:45:34 EST
References: <391@sdcjove.CAM.UNISYS.COM>
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Nf-From: ccvaxa.UUCP!aglew    Nov 27 15:11:00 1987


..> John Mashey talking about barrel architectures
Just making sure - barrel architectures are systems that multiplex
each pipeline stage between different threads of execution?
I assume this in my response.

>Assume we're using split I & D caches. Assume that the cache line
>is N words long, filled 1 word/cycle after a latency of L cycles.
>One would expect that efficient cache designs have L <= N.
I expect this is quite basic, but how do you show this for barrel
architectures (the demonstrations I've seen have required regular 
architectures).

>When filling an I-cache miss, you can do L more barrel slots,
>then you must stall for N slots (or equivalent), because it doesn't
>make sense to have the I-cache run faster than the chip (if it did,
>you would run the chip faster). 
Why not have the I-cache run faster than the chip? I-caches are more regular
structures than the cpu, and are probably that much easier to make run
faster.
    Also, why stall for N slots? There are several schemes to deliver data
from a partially filled cache line as soon as it is available. 
    Finally, why not continue on a completely separate thread while
the cache is filling for the thread that caused the cache miss?
Barrel need not imply round robin.

I think that I've missed part of John's point here.


Andy "Krazy" Glew. Gould CSD-Urbana.    1101 E. University, Urbana, IL 61801   
aglew@mycroft.gould.com    ihnp4!uiucdcs!ccvaxa!aglew    aglew@gswd-vms.arpa
   
My opinions are my own, and are not the opinions of my employer, or any
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