Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!uwvax!oddjob!hao!ames!elroy!mahendo!jplgodo!wlbr!scgvaxd!trwrb!aero!venera.isi.edu!sllu From: sllu@venera.isi.edu.UUCP Newsgroups: comp.lsi Subject: MOSIS TINY FRAME PADS (28PC23x34 FRAME) Message-ID: <4218@venera.isi.edu> Date: Tue, 1-Dec-87 20:49:13 EST Article-I.D.: venera.4218 Posted: Tue Dec 1 20:49:13 1987 Date-Received: Sun, 6-Dec-87 16:17:19 EST Organization: USC-Information Sciences Institute Lines: 28 Keywords: Magic DRC violations, I/O pad drivers, MOSIS, VLSI class Dear MOSIS users, There has been some confusion as to why MOSIS is distributing a set of pads for her TINY CHIP frame (28pc23x34) with Magic (Berkeley VLSI layout tool) design rule checker (DRC) violations. First of all, these DRC violations are known to MOSIS. Furthermore these violations cannot be easily (safely) avoided. The particular violation - "This layer can't abut or partially overlap between subcells" in question will NOT cause any electrical NOR geometrical problem. Making the contacts twice the original size (so that the contacts are completely overlaped) will eliminate the DRC violation, but WILL cause more serious electrical problems. This problem will be flagged as a CIF generation error in Magic. The other group of DRC violations has to do with P+ select layers (which are automatically generated by Magic) getting too close to transistor channels. There are 16 pieces of diffusion layers used as shields to block the bloating of P+ selects. These diffusions does not have to follow the rules. If there are further questions, please feel free to send me e-mail or post them on the net. Shih-Lien Lu for MOSIS ARPA: sllu@mosis.edu USEnet: ...!seismo!sllu@mosis.edu