Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!texsun!convex!authorplaceholder From: barr@convex.UUCP Newsgroups: comp.arch Subject: Re: VME/68020 Multiprocessor boards Message-ID: <63900009@convex> Date: Fri, 6-Nov-87 12:23:00 EST Article-I.D.: convex.63900009 Posted: Fri Nov 6 12:23:00 1987 Date-Received: Thu, 3-Dec-87 21:49:03 EST References: <44165@beno.seismo.CSS.GOV> Lines: 24 Nf-ID: #R:beno.seismo.CSS.GOV:-4416500:convex:63900009:000:1244 Nf-From: convex.UUCP!barr Nov 6 11:23:00 1987 As far as choice of cpu and controller, you really need to eval- uate the alternatives based upon the features and performance required by your particular application. I was rather surprised to hear the extreme bias towards Ciprico over Interphase in a previous posting. My experience with both companies' SMD disk products has been good, neither product appears to be "junk". I'd like to hear grenley@nsc justify that statement with some performance or reliability numbers. The choice of backplane is very important. Be aware that there is a problem inherent to VMEbus systems that manifests itself as a noise hit on the bus arbitration lines, and it is most severe for 32-bit operation. See the September `86 issue of DIGITAL DESIGN, "Switching Transients in Microcomputer System Buses", and the April 30 '87 issue of EDN, "Simple Solution Cures Glitches on High-Speed Buses" for descriptions of the problem and some recommended solutions. Backplanes are available that isolate the A, B, and C signal rows each in it's own layer with ground plane in between, and also run ground between each signal trace in a particular layer. Don't ignore the electrical characteristics of the backplane, especially in a high-performance application.