Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!mit-eddie!ll-xn!ames!ucbcad!ucbvax!M.CS.UIUC.EDU!wittaya From: wittaya@M.CS.UIUC.EDU (Wittaya Watcharawittayakul) Newsgroups: comp.sys.pyramid Subject: (none) Message-ID: <8712072224.AA16560@m.cs.uiuc.edu> Date: Mon, 7-Dec-87 17:24:40 EST Article-I.D.: m.8712072224.AA16560 Posted: Mon Dec 7 17:24:40 1987 Date-Received: Sun, 13-Dec-87 10:29:06 EST Sender: usenet@ucbvax.BERKELEY.EDU Organization: The ARPA Internet Lines: 16 I am wondering if anybody could help me with the following 90X questions : 1. How is the multiple register set managed? Is it a stack cache? Does it exist in the later model? 2. Execution time, in term of number of cycles, for the instruction set as well as detail of the processor; e.g. how it is pipelined. I realize that the information may be proprietary but I need it for simulating a machine with similar register file management for my thesis. I would appreciate any suggestion. wittaya@uiucdcsm 1304 W. Springfield Ave. Dept of Computer Science Urbana, IL 61801