Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!bbn!uwmcsd1!uwmacc!uwvax!astroatc!johnw From: johnw@astroatc.UUCP (John F. Wardale) Newsgroups: comp.arch Subject: SRAMS vs. cache-cihps (was Re: Horizontal Pipelining -- a pair) Message-ID: <636@astroatc.UUCP> Date: Tue, 8-Dec-87 14:25:34 EST Article-I.D.: astroatc.636 Posted: Tue Dec 8 14:25:34 1987 Date-Received: Sun, 13-Dec-87 15:44:02 EST References: <391@sdcjove.CAM.UNISYS.COM> <28200073@ccvaxa> <1007@winchester.UUCP> Reply-To: johnw@astroatc.UUCP (John F. Wardale) Organization: Astronautics Technology Cntr, Madison, WI Lines: 23 John Mashey, (who is alway interesting) writes: > Of delivered RISC machines, the ones that use standard >SRAMs {MIPS, SPARC} outperform those that have special-purpose >cache-mmu chips {Clipper}. The AMD29000 (no special RAM chip designs) >and Motorola 78000 {cache/mmu chips} will add a few more data points. I always thought that the "problem" with the clipper was that its path to memory was too long: (long latency Virtual-addr to data-available). Is this an affect of the cach/mmu chips, or a more seperable issue. In otherwords, can one make a good, fast RISC box with mmu/chace chips, and still maintain good memory-responce (ala MIPS and maybe AMD29000)? Any opinions, net-speculation, etc.?? (John Mashey--comment?) -- John Wardale ... {seismo | harvard | ihnp4} ! {uwvax | cs.wisc.edu} ! astroatc!johnw To err is human, to really foul up world news requires the net!