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From: baum@apple.UUCP
Newsgroups: comp.arch
Subject: Re: Wirth's challenge (was Re: RISC)
Message-ID: <6900@apple.UUCP>
Date: Fri, 4-Dec-87 15:37:01 EST
Article-I.D.: apple.6900
Posted: Fri Dec  4 15:37:01 1987
Date-Received: Tue, 8-Dec-87 03:47:33 EST
References: <902@mips.UUCP> <1775@cognos.UUCP> <5157@columbia.edu>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 39

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[]
>In article <1047@winchester.UUCP> mash@winchester.UUCP (John Mashey) writes:

>Sorry, I meant absolutely no hint that proprietary info got moved,
>and I did mean in spirit, especially of methodology of starting with
>serious optimizing compiler technology and doing substantial analysis.
>It is extremely interesting that there was no influence from the
>March 1982 Radin paper at ASPLOS; I would have thought that it would have
>been analyzed thoroughly at least for confirmation of direction,
>but I wasn't there, so I believe you.
>
>Certainly, it is interesting that both 801 and Spectrum used
>optimizing compiler-driven design,
>32 registers,
>32-bit instructions,
>separate I&D caches,
>and no windows.
>(MIPS can't be included as independent: we certainly had access to the
>published 801 documents before we started.)
>
>Either the similarities arise from the limited choices once you've
>made some of those decisions, or, starting from some of the same assumptions,
>and proceeding with realted methodologies, you get to somewhat similar
>designs.  [There are of course all sorts of little differences amongst
>the 3 machines mentioned, but if you take the universe of RISC machines,
>they look more similar than most.]

I think you hit it right on the head. We did indeed use the ASPLOS papers for
confirmation of our intuition & measurements, but they only confirmed, so 
nothing got changed. We did see some differences, but we liked our approach
(for better or worse), so no differences there either. We did have a chance
to consider register windows, since the RISC I papers were published by then,
but decided that for future implementations, the large register file, and its
decoding would be a bottleneck (impact critical path), and that smart register
allocation would be sufficient.


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