Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!linus!wivax!decvax!decwrl!sun!megatest!dre From: dre@megatest.UUCP Newsgroups: net.arch Subject: CRAY 1 Message-ID: <204@megatest.UUCP> Date: Wed, 15-Jun-83 14:48:57 EDT Article-I.D.: megatest.204 Posted: Wed Jun 15 14:48:57 1983 Date-Received: Thu, 16-Jun-83 21:14:56 EDT Lines: 24 At the time of the development of the Cray-1 the 100K ECL family did not exist, nor did the ECL gate arrays we have today. The primary logic element in the Cray 1 is the 1688 MECL III 4-5 input OR-NOR gate. This was the only subnanosecond gate that was multiply sourced at the time. An ECL gate consists of a differential amplifier with emitter follower buffered outputs. This has the characteristic that there is no difference in propagation delay between the inverting and non-inverting outputs. Thus if both outputs are terminated the device presents a purely resistive load to the power supply because there are no current spikes. Packaging density was achieved by using flatpackages attached to a ceramic carrier which I believe held something like 100 chips. Cooling was a major engineering problem on the Cray 1 and was accomplished by using Freon pumped through extruded aluminum conduit. I believe they had a difficult time developing conduit that didn't fail. One other note: NAND is a dirty word to an ECL designer! The function is achieved by wire-ORing inverters, of course. Dave Emberson Megatest Corp. Sunnyvale, CA megatest!dre