| |
|
[General Information]
|
| Processor Name: | AMD Turion64 X2 TL-60
|
| Original Processor Frequency: | 2000.0 MHz
|
| Original Processor Frequency [MHz]: | 2000
|
| |
|
| CPU ID: | 00060F82
|
| Extended CPU ID: | 00060F82
|
| CPU Brand Name: | AMD Turion(tm) 64 X2 TL-60
|
| CPU Vendor: | AuthenticAMD
|
| CPU Stepping: | BH-G2
|
| CPU Code Name: | Tyler
|
| CPU Technology: | 65 nm
|
| CPU Platform: | Socket S1g1
|
| |
|
| Number of CPU Cores: | 2
|
| Number of Logical CPUs: | 2
|
| |
|
[Operating Points]
|
| CPU Base: | 2000.0 MHz = 10.00 x 200.0 MHz @ 1.1250 V
|
| CPU Current: | 2000.1 MHz = 10.00 x 200.0 MHz @ 1.0750 V
|
| |
|
| CPU Bus Type: | Hyper-Transport v1.02
|
| Maximum Supported Hyper-Transport Link Clock: | 800 MHz
|
| Current Hyper-Transport Link Clock: | 800 MHz
|
| |
|
[Cache and TLB]
|
| L1 Cache: | Instruction: 2 x 64 KBytes, Data: 2 x 64 KBytes
|
| L2 Cache: | Integrated: 2 x 512 KBytes
|
| Instruction TLB: | Fully associative, 32 entries
|
| Data TLB: | Fully associative, 32 entries
|
| |
|
[Standard Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| Pentium-style Model Specific Registers | Present
|
| Physical Address Extension | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip / PGE (AMD) | Present
|
| Fast System Call | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Processor Number | Not Present
|
| CLFLUSH Instruction | Present
|
| Debug Trace and EMON Store | Not Present
|
| Internal ACPI Support | Not Present
|
| MMX Technology | Present
|
| Fast FP Save/Restore (IA MMX-2) | Present
|
| Streaming SIMD Extensions | Present
|
| Streaming SIMD Extensions 2 | Present
|
| Self-Snoop | Not Present
|
| Multi-Threading Capable | Present
|
| Automatic Clock Control | Not Present
|
| IA-64 Processor | Not Present
|
| Signal Break on FERR | Not Present
|
| Streaming SIMD Extensions 3 | Present
|
| PCLMULQDQ Instruction Support | Not Present
|
| MONITOR/MWAIT Support | Not Present
|
| Supplemental Streaming SIMD Extensions 3 | Not Present
|
| FMA Extension | Not Present
|
| CMPXCHG16B Support | Present
|
| Streaming SIMD Extensions 4.1 | Not Present
|
| Streaming SIMD Extensions 4.2 | Not Present
|
| x2APIC | Not Present
|
| POPCNT Instruction | Not Present
|
| AES Cryptography Support | Not Present
|
| XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Not Present
|
| XGETBV/XSETBV OS Enabled | Not Present
|
| AVX Support | Not Present
|
| Half-Precision Convert (CVT16) | Not Present
|
[Extended Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| AMD-style Model Specific Registers | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip | Present
|
| SYSCALL and SYSRET Instructions | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Multi-Processing / Brand feature | Not Present
|
| No Execute | Present
|
| MMX Technology | Present
|
| MMX+ Extensions | Present
|
| Fast FP Save/Restore | Present
|
| Fast FP Save/Restore Optimizations | Present
|
| 1 GB large page support | Not Present
|
| RDTSCP Instruction | Present
|
| x86-64 Long Mode | Present
|
| 3DNow! Technology Extensions | Present
|
| 3DNow! Technology | Present
|
| LAHF/SAHF Long Mode Support | Present
|
| Core Multi-Processing Legacy Mode | Present
|
| Secure Virtual Machine | Present
|
| Extended APIC Register Space | Present
|
| LOCK MOV CR0 Support | Present
|
| Advanced Bit Manipulation | Not Present
|
| SSE4A Support | Not Present
|
| Misaligned SSE Mode | Not Present
|
| PREFETCH(W) Support | Present
|
| OS Visible Work-around Support | Not Present
|
| Instruction Based Sampling | Not Present
|
| XOP Instruction Support | Not Present
|
| SKINIT, STGI, and DEV Support | Not Present
|
| Watchdog Timer Support | Not Present
|
| TBM0 Instruction Support | Not Present
|
| Lightweight Profiling Support | Not Present
|
| FMA4 Instruction Support | Not Present
|
| Translation Cache Extension | Not Present
|
| NodeId Support | Not Present
|
| Trailing Bit Manipulation | Not Present
|
| Topology Extensions | Not Present
|
| Core Performance Counter Extensions | Not Present
|
| NB Performance Counter Extensions | Not Present
|
| Streaming Performance Monitor Architecture | Not Present
|
| Data Breakpoint Extension | Not Present
|
| Performance Time-Stamp Counter | Not Present
|
| L2I Performance Counter Extensions | Not Present
|
| MWAITX/MONITORX Support | Not Present
|
| Secure Memory Encryption | Not Present
|
| Secure Encrypted Virtualization | Not Present
|
| |
|
[Enhanced Features]
|
| Core Performance Boost | Not Supported
|
| |
|
[Memory Ranges]
|
| Maximum Physical Address Size: | 40-bit (1 TBytes)
|
| Maximum Virtual Address Size: | 48-bit (256 TBytes)
|
[MTRRs]
|
| Range 0-80000000 (0MB-2048MB) Type: | Write Back (WB)
|
| |
|
[General Information]
|
| Device Name: | AMD Hammer - HyperTransport Technology Configuration
|
| Original Device Name: | AMD Hammer - HyperTransport Technology Configuration
|
| Device Class: | Host-to-PCI Bridge
|
| Revision ID: | 0
|
| PCI Address (Bus:Device:Function) Number: | 0:24:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1022&DEV_1100&SUBSYS_00000000&REV_00
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| |
|
[Features]
|
| Bus Mastering: | Disabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| |
|
[Driver Information]
|
| Driver Manufacturer: | AMD
|
| Driver Description: | AMD HyperTransport(tm) Configuration
|
| Driver Provider: | Microsoft
|
| Driver Version: | 6.1.7601.17514
|
| Driver Date: | 20-Jun-2006
|
| DeviceInstanceId | PCI\VEN_1022&DEV_1100&SUBSYS_00000000&REV_00\3&a mp;2411E6FE&2&C0
|
| Location Paths | PCIROOT(0)#PCI(1800)
|
| |
|
[Routing Node 0]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 1]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 2]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 3
]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 4]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 5]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 6]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Routing Node 7]
|
| Request Route: | This node
|
| Response Route: | This node
|
| Broadcast Route: | This node
|
| |
|
[Node ID]
|
| This Node ID: | 0
|
| Node Count: | 1
|
| HyperTransport I/O Hub Node ID: | 0
|
| Lock Controller Node ID: | 0
|
| CPU Count: | 2
|
| |
|
[Unit ID]
|
| CPU0 Unit ID: | 0
|
| CPU1 Unit ID: | 1
|
| Memory Controller Unit ID: | 2
|
| Host Bridge Unit ID: | 3
|
| HyperTransport I/O Hub Link ID: | LDT0
|
| |
|
[HyperTransport Transaction Control]
|
| Medium priority isochronous writes: | Enabled
|
| High priority isochronous writes: | Enabled
|
| Low priority writes: | Enabled
|
| High priority CPU reads: | Disabled
|
| High-priority bypass count: | 3
|
| Medium-priority bypass count: | 3
|
| Downstream non-posted request limit: | 1
|
| Sequence ID source node: | Disabled
|
| APIC extended spurious vector: | Writable
|
| APIC extended ID: | 8 bits
|
| APIC extended broadcast ID: | FFh
|
| Local interrupt conversion: | Disabled
|
| Coherent HyperTransport configuration space range: | Limited
|
| Buffer release priority select: | 8 packets
|
| Change ISOC to Ordered: | Isochronous prioritization
|
| Response PassPW: | Enabled
|
| Fill probe: | Enabled
|
| Remote probe memory cancel: | Enabled
|
| Probe memory cancel: | Enabled
|
| CPU Read response PassPW: | Disabled
|
| CPU request PassPW: | Disabled
|
| CPU1: | Enabled
|
| Memory controller target start: | Enabled
|
| Write doubleword probes: | Enabled
|
| Write byte probes: | Enabled
|
| Read doubleword probe: | Enabled
|
| Read byte probe: | Enabled
|
| |
|
[HyperTransport Initialization Control]
|
| Default Link: | CPU on same node
|
| Request: | Enabled
|
| Routing Table: | Enabled
|
| |
|
[LDT0 Capability]
|
| Drop on Uninitialized Link: | No
|
| Inbound End-of-Chain Error: | No
|
| Act As Slave: | No
|
| Host Hide: | Yes
|
| Chain Side: | 0
|
| Device Number: | 0
|
| Double Ended: | No
|
| |
|
[LDT0 Link Control]
|
| Doubleword Flow Control Out: | Disabled
|
| Link Width Out: | 16 bits
|
| Doubleword Flow Control In: | Disabled
|
| Link Width In: | 16 bits
|
| Doubleword Flow Control Out: | Not supported
|
| Max. Link Width Out: | 16 bits
|
| Doubleword Flow Control In: | Not supported
|
| Max. Link Width In: | 16 bits
|
| Extended Control Time During Initialization: | >=16 bit times
|
| HyperTransport Stop Tristate: | Enabled
|
| Isochronous: | Disabled
|
| CRC Error On Incoming Link (Higher Byte): | Not detected
|
| CRC Error On Incoming Link (Lower Byte): | Not detected
|
| Transmitter: | On
|
| Receiver: | On
|
| Initialization Complete: | Yes
|
| Link Failure: | Not detected
|
| CRC Flood: | Disabled
|
| |
|
[LDT0 Link Frequency Capability]
|
| Link 200 MHz Frequency Capability: | Capable
|
| Link 300 MHz Frequency Capability: | Not capable
|
| Link 400 MHz Frequency Capability: | Capable
|
| Link 500 MHz Frequency Capability: | Not capable
|
| Link 600 MHz Frequency Capability: | Capable
|
| Link 800 MHz Frequency Capability: | Capable
|
| Link 1000 MHz Frequency Capability: | Not capable
|
| Link 1200 MHz Frequency Capability: | Not capable
|
| Link 1400 MHz Frequency Capability: | Not capable
|
| Link 1600 MHz Frequency Capability: | Not capable
|
| Link 1800 MHz Frequency Capability: | Not capable
|
| Link 2000 MHz Frequency Capability: | Not capable
|
| Link 2200 MHz Frequency Capability: | Not capable
|
| Link 2400 MHz Frequency Capability: | Not capable
|
| Link 2600 MHz Frequency Capability: | Not capable
|
| Link 100 MHz Frequency Capability: | Capable
|
| Current Link Frequency: | 800 MHz
|
| Link Major Revision: | 1
|
| Link Minor Revision: | 2
|
| |
|
[LDT0 Feature Capability]
|
| Extended Register Set: | Not supported
|
| Extended CTL: | Not required
|
| CRC Test Mode: | Not supported
|
| HyperTransport Stop Mode: | Supported
|
| Isochronous Flow Control Mode: | Not supported
|
| |
|
[LDT0 Buffer Count]
|
| Response Data Buffer Count: | 1
|
| Posted Request Data Buffer Count: | 6
|
| Request Data Buffer Count: | 1
|
| Probe Buffer Count: | 0
|
| Response Buffer Count: | 1
|
| Posted Request Buffer Count: | 6
|
| Request Buffer Count: | 9
|
| |
|
[LDT0 Bus Number]
|
| Subordinate Bus Number: | 255
|
| Secondary Bus Number: | 0
|
| Primary Bus Number: | 0
|
| |
|
[LDT0 Type]
|
| Link Connect Pending: | No
|
| UniP-cLDT: | Normal coherent/Noncoherent
|
| Non Coherent: | Noncoherent technology
|
| Initialization Complete: | Yes
|
| Link Connect Status: | Connected
|
| |
|
[LDT1 Capability]
|
| Drop on Uninitialized Link: | No
|
| Inbound End-of-Chain Error: | No
|
| Act As Slave: | No
|
| Host Hide: | No
|
| Chain Side: | 0
|
| Device Number: | 0
|
| Double Ended: | No
|
| |
|
[LDT1 Link Control]
|
| Doubleword Flow Control Out: | Disabled
|
| Link Width Out: | 8 bits
|
| Doubleword Flow Control In: | Disabled
|
| Link Width In: | 8 bits
|
| Doubleword Flow Control Out: | Not supported
|
| Max. Link Width Out: | 8 bits
|
| Doubleword Flow Control In: | Not supported
|
| Max. Link Width In: | 8 bits
|
| Extended Control Time During Initialization: | >=16 bit times
|
| HyperTransport Stop Tristate: | Disabled
|
| Isochronous: | Disabled
|
| CRC Error On Incoming Link (Higher Byte): | Not detected
|
| CRC Error On Incoming Link (Lower Byte): | Not detected
|
| Transmitter: | On
|
| Receiver: | On
|
| Initialization Complete: | No
|
| Link Failure: | Not detected
|
| CRC Flood: | Disabled
|
| |
|
[LDT1 Link Frequency Capability]
|
| Link 200 MHz Frequency Capability: | Not capable
|
| Link 300 MHz Frequency Capability: | Not capable
|
| Link 400 MHz Frequency Capability: | Not capable
|
| Link 500 MHz Frequency Capability: | Not capable
|
| Link 600 MHz Frequency Capability: | Not capable
|
| Link 800 MHz Frequency Capability: | Not capable
|
| Link 1000 MHz Frequency Capability: | Not capable
|
| Link 1200 MHz Frequency Capability: | Not capable
|
| Link 1400 MHz Frequency Capability: | Not capable
|
| Link 1600 MHz Frequency Capability: | Not capable
|
| Link 1800 MHz Frequency Capability: | Not capable
|
| Link 2000 MHz Frequency Capability: | Not capable
|
| Link 2200 MHz Frequency Capability: | Not capable
|
| Link 2400 MHz Frequency Capability: | Not capable
|
| Link 2600 MHz Frequency Capability: | Not capable
|
| Link 100 MHz Frequency Capability: | Not capable
|
| Current Link Frequency: | 200 MHz
|
| Link Major Revision: | 0
|
| Link Minor Revision: | 0
|
| |
|
[LDT1 Feature Capability]
|
| Extended Register Set: | Not supported
|
| Extended CTL: | Not required
|
| CRC Test Mode: | Not supported
|
| HyperTransport Stop Mode: | Not supported
|
| Isochronous Flow Control Mode: | Not supported
|
| |
|
[LDT1 Buffer Count]
|
| Response Data Buffer Count: | 0
|
| Posted Request Data Buffer Count: | 0
|
| Request Data Buffer Count: | 0
|
| Probe Buffer Count: | 0
|
| Response Buffer Count: | 0
|
| Posted Request Buffer Count: | 0
|
| Request Buffer Count: | 0
|
| |
|
[LDT1 Bus Number]
|
| Subordinate Bus Number: | 0
|
| Secondary Bus Number: | 0
|
| Primary Bus Number: | 0
|
| |
|
[LDT1 Type]
|
| Link Connect Pending: | No
|
| UniP-cLDT: | Normal coherent/Noncoherent
|
| Non Coherent: | Coherent technology
|
| Initialization Complete: | No
|
| Link Connect Status: | Not connected
|
| |
|
[LDT2 Capability]
|
| Drop on Uninitialized Link: | No
|
| Inbound End-of-Chain Error: | No
|
| Act As Slave: | No
|
| Host Hide: | No
|
| Chain Side: | 0
|
| Device Number: | 0
|
| Double Ended: | No
|
| |
|
[LDT2 Link Control]
|
| Doubleword Flow Control Out: | Disabled
|
| Link Width Out: | 8 bits
|
| Doubleword Flow Control In: | Disabled
|
| Link Width In: | 8 bits
|
| Doubleword Flow Control Out: | Not supported
|
| Max. Link Width Out: | 8 bits
|
| Doubleword Flow Control In: | Not supported
|
| Max. Link Width In: | 8 bits
|
| Extended Control Time During Initialization: | >=16 bit times
|
| HyperTransport Stop Tristate: | Disabled
|
| Isochronous: | Disabled
|
| CRC Error On Incoming Link (Higher Byte): | Not detected
|
| CRC Error On Incoming Link (Lower Byte): | Not detected
|
| Transmitter: | On
|
| Receiver: | On
|
| Initialization Complete: | No
|
| Link Failure: | Not detected
|
| CRC Flood: | Disabled
|
| |
|
[LDT2 Link Frequency Capability]
|
| Link 200 MHz Frequency Capability: | Not capable
|
| Link 300 MHz Frequency Capability: | Not capable
|
| Link 400 MHz Frequency Capability: | Not capable
|
| Link 500 MHz Frequency Capability: | Not capable
|
| Link 600 MHz Frequency Capability: | Not capable
|
| Link 800 MHz Frequency Capability: | Not capable
|
| Link 1000 MHz Frequency Capability: | Not capable
|
| Link 1200 MHz Frequency Capability: | Not capable
|
| Link 1400 MHz Frequency Capability: | Not capable
|
| Link 1600 MHz Frequency Capability: | Not capable
|
| Link 1800 MHz Frequency Capability: | Not capable
|
| Link 2000 MHz Frequency Capability: | Not capable
|
| Link 2200 MHz Frequency Capability: | Not capable
|
| Link 2400 MHz Frequency Capability: | Not capable
|
| Link 2600 MHz Frequency Capability: | Not capable
|
| Link 100 MHz Frequency Capability: | Not capable
|
| Current Link Frequency: | 200 MHz
|
| Link Major Revision: | 0
|
| Link Minor Revision: | 0
|
| |
|
[LDT2 Feature Capability]
|
| Extended Register Set: | Not supported
|
| Extended CTL: | Not required
|
| CRC Test Mode: | Not supported
|
| HyperTransport Stop Mode: | Not supported
|
| Isochronous Flow Control Mode: | Not supported
|
| |
|
[LDT2 Buffer Count]
|
| Response Data Buffer Count: | 0
|
| Posted Request Data Buffer Count: | 0
|
| Request Data Buffer Count: | 0
|
| Probe Buffer Count: | 0
|
| Response Buffer Count: | 0
|
| Posted Request Buffer Count: | 0
|
| Request Buffer Count: | 0
|
| |
|
[LDT2 Bus Number]
|
| Subordinate Bus Number: | 0
|
| Secondary Bus Number: | 0
|
| Primary Bus Number: | 0
|
| |
|
[LDT2 Type]
|
| Link Connect Pending: | No
|
| UniP-cLDT: | Normal coherent/Noncoherent
|
| Non Coherent: | Coherent technology
|
| Initialization Complete: | No
|
| Link Connect Status: | Not connected
|
| |
|
[General Information]
|
| Device Name: | AMD Hammer - Address Map
|
| Original Device Name: | AMD Hammer - Address Map
|
| Device Class: | Host-to-PCI Bridge
|
| Revision ID: | 0
|
| PCI Address (Bus:Device:Function) Number: | 0:24:1
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1022&DEV_1101&SUBSYS_00000000&REV_00
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| |
|
[Features]
|
| Bus Mastering: | Disabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| |
|
[Driver Information]
|
| Driver Manufacturer: | AMD
|
| Driver Description: | AMD Address Map Configuration
|
| Driver Provider: | Microsoft
|
| Driver Version: | 6.1.7601.17514
|
| Driver Date: | 20-Jun-2006
|
| DeviceInstanceId | PCI\VEN_1022&DEV_1101&SUBSYS_00000000&REV_00\3&a mp;2411E6FE&2&C1
|
| Location Paths | PCIROOT(0)#PCI(1801)
|
| |
|
[DRAM Base 0]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | Read/Write
|
| |
|
[DRAM Limit 0]
|
| DRAM Limit Address: | 7F000000
|
| Interleave: | None
|
| Destination Node ID: | 0
|
| |
|
[DRAM Base 1]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 1]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 1
|
| |
|
[DRAM Base 2]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 2]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 2
|
| |
|
[DRAM Base 3]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 3]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 3
|
| |
|
[DRAM Base 4]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 4]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 4
|
| |
|
[DRAM Base 5]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 5]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 5
|
| |
|
[DRAM Base 6]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 6]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 6
|
| |
|
[DRAM Base 7]
|
| DRAM Base Address: | 000
|
| Interleave: | None
|
| Access: | No access
|
| |
|
[DRAM Limit 7]
|
| DRAM Limit Address: | 000
|
| Interleave: | None
|
| Destination Node ID: | 7
|
| |
|
[Memory-Mapped I/O Base 0]
|
| Memory-Mapped I/O Base Address: | 000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | No access
|
| |
|
[Memory-Mapped I/O Limit 0]
|
| Memory-Mapped I/O Limit Address: | 000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 1]
|
| Memory-Mapped I/O Base Address: | 000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | No access
|
| |
|
[Memory-Mapped I/O Limit 1]
|
| Memory-Mapped I/O Limit Address: | 000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 2]
|
| Memory-Mapped I/O Base Address: | 000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | No access
|
| |
|
[Memory-Mapped I/O Limit 2]
|
| Memory-Mapped I/O Limit Address: | 000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 3]
|
| Memory-Mapped I/O Base Address: | 000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | No access
|
| |
|
[Memory-Mapped I/O Limit 3]
|
| Memory-Mapped I/O Limit Address: | 000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 4]
|
| Memory-Mapped I/O Base Address: | A0000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | Read/Write
|
| |
|
[Memory-Mapped I/O Limit 4]
|
| Memory-Mapped I/O Limit Address: | B0000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 5]
|
| Memory-Mapped I/O Base Address: | 80000000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | Read/Write
|
| |
|
[Memory-Mapped I/O Limit 5]
|
| Memory-Mapped I/O Limit Address: | DFFF0000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 6]
|
| Memory-Mapped I/O Base Address: | E0000000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | Read/Write
|
| |
|
[Memory-Mapped I/O Limit 6]
|
| Memory-Mapped I/O Limit Address: | EFFF0000
|
| Non-Posted: | Non-Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Memory-Mapped I/O Base 7]
|
| Memory-Mapped I/O Base Address: | F0000000
|
| Lock: | Unlocked
|
| CPU Access: | Enabled
|
| Access: | Read/Write
|
| |
|
[Memory-Mapped I/O Limit 7]
|
| Memory-Mapped I/O Limit Address: | FE0B0000
|
| Non-Posted: | Posted
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[PCI I/O Base 0]
|
| PCI I/O Base Address: | 0
|
| ISA Enable: | Disabled
|
| VGA Enable: | Disabled
|
| Access: | No access
|
| |
|
[PCI I/O Limit 0]
|
| PCI I/O Limit Address: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[PCI I/O Base 1]
|
| PCI I/O Base Address: | 1
|
| ISA Enable: | Disabled
|
| VGA Enable: | Enabled
|
| Access: | Read/Write
|
| |
|
[PCI I/O Limit 1]
|
| PCI I/O Limit Address: | FF
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[PCI I/O Base 2]
|
| PCI I/O Base Address: | 0
|
| ISA Enable: | Disabled
|
| VGA Enable: | Disabled
|
| Access: | No access
|
| |
|
[PCI I/O Limit 2]
|
| PCI I/O Limit Address: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[PCI I/O Base 3]
|
| PCI I/O Base Address: | 0
|
| ISA Enable: | Disabled
|
| VGA Enable: | Disabled
|
| Access: | No access
|
| |
|
[PCI I/O Limit 3]
|
| PCI I/O Limit Address: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| |
|
[Config Base and Limit 0]
|
| Bus Number Limit: | FF
|
| Bus Number Base: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| Device Number Compare: | Disabled
|
| Access: | Read/Write
|
| |
|
[Config Base and Limit 1]
|
| Bus Number Limit: | 0
|
| Bus Number Base: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| Device Number Compare: | Disabled
|
| Access: | No access
|
| |
|
[Config Base and Limit 2]
|
| Bus Number Limit: | 0
|
| Bus Number Base: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| Device Number Compare: | Disabled
|
| Access: | No access
|
| |
|
[Config Base and Limit 3]
|
| Bus Number Limit: | 0
|
| Bus Number Base: | 0
|
| Destination Link ID: | 0
|
| Destination Node ID: | 0
|
| Device Number Compare: | Disabled
|
| Access: | No access
|
| |
|
[DRAM Hole]
|
| DRAM Hole Base Address: | 0
|
| DRAM Hole Offset: | 0
|
| DRAM Hole Enable: | Disabled
|
| |
|
[General Information]
|
| Device Name: | AMD Hammer - Miscellaneous Control
|
| Original Device Name: | AMD Hammer - Miscellaneous Control
|
| Device Class: | Host-to-PCI Bridge
|
| Revision ID: | 0
|
| PCI Address (Bus:Device:Function) Number: | 0:24:3
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1022&DEV_1103&SUBSYS_00000000&REV_00
|
| |
|
[System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| |
|
[Features]
|
| Bus Mastering: | Disabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| |
|
[Driver Information]
|
| Driver Manufacturer: | AMD
|
| Driver Description: | AMD Miscellaneous Configuration
|
| Driver Provider: | Microsoft
|
| Driver Version: | 6.1.7601.17514
|
| Driver Date: | 20-Jun-2006
|
| DeviceInstanceId | PCI\VEN_1022&DEV_1103&SUBSYS_00000000&REV_00\3&a mp;2411E6FE&2&C3
|
| Location Paths | PCIROOT(0)#PCI(1803)
|
| |
|
[MCA NB Control]
|
| DRAM Parity Error Reporting [F]: | Enabled
|
| Watchdog Timer Error Reporting: | Enabled
|
| Atomic Read-Modify-Write Error Reporting: | Enabled
|
| GART Table Walk Error Reporting: | Disabled
|
| Target Abort Error Reporting: | Enabled
|
| Master Abort Error Reporting: | Enabled
|
| HyperTransport Link 2 Sync Packet Error Reporting: | Enabled
|
| HyperTransport Link 1 Sync Packet Error Reporting: | Enabled
|
| HyperTransport Link 0 Sync Packet Error Reporting: | Enabled
|
| HyperTransport Link 2 CRC Error Reporting: | Enabled
|
| HyperTransport Link 1 CRC Error Reporting: | Enabled
|
| HyperTransport Link 0 CRC Error Reporting: | Enabled
|
| Uncorrectable ECC Error Reporting: | Enabled
|
| Correctable ECC Error Reporting: | Enabled
|
| |
|
[MCA NB Configuration]
|
| Sync Flood on DRAM Address Parity Error [F]: | Disabled
|
| Master Abort CPU Error Response [F]: | Enabled
|
| Target Abort CPU Error Response [F]: | Enabled
|
| Northbridge MCA to CPU 0: | Enabled
|
| PCI Configuration CPU Error Response: | Disabled
|
| I/O Read Data Error Log: | Disabled
|
| Chip-Kill ECC Mode: | Disabled
|
| ECC: | Disabled
|
| Sync Flood On Any Error: | Disabled
|
| Sync Flood on Watchdog Timer Error: | Enabled
|
| HyperTransport Link Select for CRC Error Generation: | Link 0
|
| Watchdog Timer Time Base: | 1 ms
|
| Watchdog Timer Count: | 4095
|
| Watchdog Timer: | Enabled
|
| I/O Error Response: | Enabled
|
| CPU Error Response: | Disabled
|
| I/O Master Abort Error Response: | Enabled
|
| Sync Packet Propagation: | Enabled
|
| Sync Packet Generation: | Enabled
|
| Sync Flood on Uncorrectable ECC Error: | Disabled
|
| CPU Read Data Error Log: | Disabled
|
| CPU ECC Error Log: | Disabled
|
| |
|
[SRI-to-XBAR Buffer Count]
|
| Downstream Posted Request Buffer Count: | 1
|
| Downstream Request Buffer Count: | 1
|
| Upstream Response Data Buffer Count: | 1
|
| Display Refresh Request Buffer Count: | 3
|
| Request Data Buffer Count: | 0
|
| Upstream Response Buffer Count: | 1
|
| Upstream Posted Request Buffer Count: | 1
|
| Upstream Request Buffer Count: | 1
|
| |
|
[XBAR-to-SRI Buffer Count]
|
| Downstream Posted Request Buffer Count: | 1
|
| Downstream Request Buffer Count: | 1
|
| Display Refresh Request Buffer Count: | 7
|
| Probe Buffer Count: | 4
|
| Upstream Posted Request Buffer Count: | 2
|
| Upstream Request Buffer Count: | 1
|
| |
|
[MCT-to-XBAR Buffer Count]
|
| Response Data Buffer Count: | 8
|
| Probe Buffer Count: | 2
|
| Response Buffer Count: | 10
|
| |
|
[Free List Buffer Count]
|
| SRI to XBAR Free Response Data Buffer Count: | 2
|
| SRI to XBAR Free Response Buffer Count: | 1
|
| SRI to XBAR Free Request Buffer Count: | 1
|
| SRI Free Command Buffer Count: | 7
|
| |
|
[Power Management Control]
|
| Power Management Mode 7 Clock Divisor: | 64
|
| Power Management Mode 7 Alternate VID Change: | Disabled
|
| Power Management Mode 7 FID/VID Change: | Disabled
|
| Power Management Mode 7 NB Low Power: | Disabled
|
| Power Management Mode 7 CPU Low Power: | Enabled
|
| Power Management Mode 6 Clock Divisor: | 16
|
| Power Management Mode 6 Alternate VID Change: | Disabled
|
| Power Management Mode 6 FID/VID Change: | Disabled
|
| Power Management Mode 6 NB Low Power: | Enabled
|
| Power Management Mode 6 CPU Low Power: | Enabled
|
| Power Management Mode 5 Clock Divisor: | 64
|
| Power Management Mode 5 Alternate VID Change: | Disabled
|
| Power Management Mode 5 FID/VID Change: | Disabled
|
| Power Management Mode 5 NB Low Power: | Disabled
|
| Power Management Mode 5 CPU Low Power: | Enabled
|
| Power Management Mode 4 Clock Divisor: | 16
|
| Power Management Mode 4 Alternate VID Change: | Disabled
|
| Power Management Mode 4 FID/VID Change: | Disabled
|
| Power Management Mode 4 NB Low Power: | Enabled
|
| Power Management Mode 4 CPU Low Power: | Enabled
|
| Power Management Mode 3 Clock Divisor: | 64
|
| Power Management Mode 3 Alternate VID Change: | Disabled
|
| Power Management Mode 3 FID/VID Change: | Disabled
|
| Power Management Mode 3 NB Low Power: | Enabled
|
| Power Management Mode 3 CPU Low Power: | Enabled
|
| Power Management Mode 2 Clock Divisor: | 8
|
| Power Management Mode 2 Alternate VID Change: | Disabled
|
| Power Management Mode 2 FID/VID Change: | Enabled
|
| Power Management Mode 2 NB Low Power: | Enabled
|
| Power Management Mode 2 CPU Low Power: | Enabled
|
| Power Management Mode 1 Clock Divisor: | 64
|
| Power Management Mode 1 Alternate VID Change: | Disabled
|
| Power Management Mode 1 FID/VID Change: | Enabled
|
| Power Management Mode 1 NB Low Power: | Enabled
|
| Power Management Mode 1 CPU Low Power: | Enabled
|
| Power Management Mode 0 Clock Divisor: | 64
|
| Power Management Mode 0 Alternate VID Change: | Disabled
|
| Power Management Mode 0 FID/VID Change: | Disabled
|
| Power Management Mode 0 NB Low Power: | Disabled
|
| Power Management Mode 0 CPU Low Power: | Enabled
|
| |
|
[GART Aperture Control]
|
| GART Table Walk Probes: | Enabled
|
| GART I/O Accesses: | Enabled
|
| GART CPU Accesses: | Enabled
|
| GART Size: | 32 MBytes
|
| GART: | Disabled
|
| |
|
[GART Aperture Base]
|
| GART Aperture Base Address: | A000000
|
| |
|
[GART Table Base]
|
| GART Table Base Address: | AA5415000
|
| |
|
[Clock Power/Timing]
|
| HyperTransport CLK PLL Lock Counter: | 13
|
| Link Reconnect Delay: | 10 us
|
| Clock Ramp Hysteresis: | 2000 ns
|
| Time to Drive Sleep VID: | 0 system clocks
|
| Good Phase Error: | 400(B)/200(C) system clocks
|
| Ramp VID Offset: | 0 mV
|
| Alternate VID: | 17
|
| Voltage Regulator Stabilization Time: | 0 ns
|
| |
|
[HyperTransportt FIFO Read Pointer Optimization]
|
| Change Read Pointer For HyperTransport Link 2 Transmitter: | Move RdPtr closer to WrPtr by 2 HyperTransport clock periods
|
| Change Read Pointer For HyperTransport Link 2 Receiver: | Move RdPtr closer to WrPtr by 6 HyperTransport clock periods
|
| Change Read Pointer For HyperTransport Link 1 Transmitter: | Move RdPtr closer to WrPtr by 2 HyperTransport clock periods
|
| Change Read Pointer For HyperTransport Link 1 Receiver: | Move RdPtr closer to WrPtr by 6 HyperTransport clock periods
|
| Change Read Pointer For HyperTransport Link 0 Transmitter: | Move RdPtr closer to WrPtr by 2 HyperTransport clock periods
|
| Change Read Pointer For HyperTransport Link 0 Receiver: | Move RdPtr closer to WrPtr by 5 HyperTransport clock periods
|
| |
|
[Thermtrip Status]
|
| Case Temperature Specification (TCaseMax) [Rev E]: | Not defined
|
| Diode Offset Sign [Rev E]: | Positive
|
| Tj Offset [Rev F]: | 0 ḞC
|
| Current Temperature [Rev F]: | 62 ḞC
|
| Diode Offset: | 14 ḞC
|
| Thermtrip Enabled: | Enabled
|
| Thermtrip Sense (Core1): | Doesn't occur
|
| Thermtrip Sense (Core0): | Doesn't occur
|
| Thermtrip Status: | Doesn't occur
|
| |
|
[Northbridge Capabilities]
|
| Multi-Core Capability: | Dual-Core
|
| HTC (Hardware Thermal Control): | Capable
|
| On-chip Memory Controller: | Capable
|
| Maximum DRAM Frequency: | No limit
|
| Chip-Kill ECC: | Not capable
|
| ECC: | Not capable
|
| Big MP: | Not capable
|
| MP: | Not capable
|
| 128-Bit DRAM: | Capable
|
| |
|
[General Information]
|
| Drive Controller: | Serial ATA 6Gb/s @ 3Gb/s
|
| Host Controller: | IDE Channel
|
| Drive Model: | WDC WD3200LPVX-75V0TT0
|
| Drive Firmware Revision: | 01.01A01
|
| Drive Serial Number: | WX41A34W2831
|
| World Wide Name: | 50014EE6AF2A44AD
|
| Drive Capacity: | 305,245 MBytes (320 GB)
|
| Drive Capacity [MB]: | 305245
|
| Media Rotation Rate: | 5400 RPM
|
| ATA Major Version Supported: | ATA/ATAPI-5, ATA/ATAPI-6, ATA/ATAPI-7, ATA8-ACS, ACS-2
|
| ATA Transport Version Supported: | SATA 3.0
|
| |
|
[Drive Geometry]
|
| Number of Cylinders: | 16383
|
| Number of Heads: | 16
|
| Sectors Per Track: | 63
|
| Number of Sectors: | 16514064
|
| Total 48-bit LBA Sectors: | 625142448
|
| Logical Sector Size: | 512 Bytes
|
| Cache Buffer Size: | 8192 KBytes
|
| |
|
[Transfer Modes]
|
| Sectors Per Interrupt: | Total: 16, Active: 16
|
| Max. PIO Transfer Mode: | 4
|
| Multiword DMA Mode: | Total: 2, Active: -
|
| Singleword DMA Mode: | Total: -, Active: -
|
| Ultra-DMA Mode: | Total: 6 (ATA-133), Active: 6 (ATA-133)
|
| Max. Multiword DMA Transfer Rate: | 16.7 MBytes/s
|
| Max. PIO with IORDY Transfer Rate: | 16.7 MBytes/s
|
| Max. PIO w/o IORDY Transfer Rate: | 16.7 MBytes/s
|
| Native Command Queuing: | Supported, Max. Depth: 32
|
| TRIM Command: | Not Supported
|
| |
|
[Device flags]
|
| Fixed Drive: | Present
|
| Removable Drive: | Not Present
|
| Magnetic Storage: | Present
|
| LBA Mode: | Supported
|
| DMA Mode: | Supported
|
| IORDY: | Supported
|
| IORDY Disableable: | Supported
|
| |
|
[Features]
|
| Write Cache: | Present, Active
|
| S.M.A.R.T. Feature: | Present, Active
|
| Security Feature: | Present, Inactive
|
| Removable Media Feature: | Not Present, Disabled
|
| Power Management: | Present, Active
|
| Advanced Power Management: | Present, Active
|
| Packet Interface: | Not Present, Disabled
|
| Look-Ahead Buffer: | Present, Active
|
| Host Protected Area: | Present, Enabled
|
| Power-Up In Standby: | Supported, Inactive
|
| Automatic Acoustic Management: | Not Suppported, Inactive
|
| 48-bit LBA: | Supported, Active
|
| Host-Initiated Link Power Management: | Supported
|
| Device-Initiated Link Power Management: | Supported, Disabled
|
| In-Order Data Delivery: | Not Supported
|
| Hardware Feature Control: | Not Supported
|
| Software Settings Preservation: | Supported, Enabled
|
| NCQ Autosense: | Not Supported
|
| Link Power State Device Sleep: | Not Supported
|
| Hybrid Information Feature: | Not Supported
|
| Rebuild Assist: | Not Supported
|
| Power Disable: | Not Supported
|
| All Write Cache Non-Volatile: | Not Supported
|
| Extended Number of User Addressable Sectors: | Not Supported
|
| CFast Specification: | Not Supported
|
| NCQ Priority Information: | Supported
|
| Host Automatic Partial to Slumber Transitions: | Supported
|
| Device Automatic Partial to Slumber Transitions: | Supported
|
| NCQ Streaming: | Not Supported
|
| NCQ Queue Management Command: | Not Supported
|
| DevSleep to Reduced Power State: | Not Supported
|
| Out Of Band Management Interface: | Not Supported
|
| Extended Power Conditions Feature: | Not Supported
|
| Sense Data Reporting Feature: | Not Supported
|
| Free-Fall Control Feature: | Not Supported
|
| Write-Read-Verify Feature: | Not Supported
|
| |
|
[Security]
|
| Security Feature: | Supported
|
| Security Status: | Disabled
|
| Security Locked: | Disabled
|
| Security Frozen: | Enabled
|
| Enhanced Security Erase: | Supported
|
| Sanitize Feature: | Not Supported
|
| Sanitize Device - Crypto Scramble: | Not Supported
|
| Sanitize Device - Overwrite: | Not Supported
|
| Sanitize Device - Block Erase: | Not Supported
|
| Sanitize Device - Antifreeze Lock: | Not Supported
|
| Device Encrypts All User Data: | Not Supported
|
| Trusted Computing: | Not Supported
|
| |
|
[Self-Monitoring, Analysis and Reporting Technology (S.M.A.R.T.)]
|
| [01] Raw Read Error Rate: | 200/51, Worst: 200 (Data = 4,0)
|
| [03] Spin Up Time: | 152/21, Worst: 150 (Data = 1383,0)
|
| [04] Start/Stop Count: | 100/Always OK, Worst: 100 (Data = 847,0)
|
| [05] Reallocated Sector Count: | 200/140, Worst: 200
|
| [07] Seek Error Rate: | 200/Always OK, Worst: 200
|
| [09] Power-On Hours/Cycle Count: | 97/Always OK, Worst: 97 (2720 hours / 113.3 days)
|
| [0A] Spin Retry Count: | 100/Always OK, Worst: 100
|
| [0B] Calibration Retry Count: | 100/Always OK, Worst: 100
|
| [0C] Power Cycle Count: | 100/Always OK, Worst: 100 (Data = 732,0)
|
| [BF] G-Sense Error Rate: | 31/Always OK, Worst: 31 (Data = 69,0)
|
| [C0] Power-Off Retract Count: | 200/Always OK, Worst: 200 (Data = 51,0)
|
| [C1] Load/Unload Cycle Count: | 186/Always OK, Worst: 186 (Data = 44204,0)
|
| [C2] Temperature | 114/Always OK, Worst: 78 (29.0 ḞC)
|
| [C4] Reallocation Event Count: | 200/Always OK, Worst: 200
|
| [C5] Current Pending Sector Count: | 200/Always OK, Worst: 200
|
| [C6] Off-Line Uncorrectable Sector Count: | 100/Always OK, Worst: 253
|
| [C7] UltraDMA/SATA CRC Error Rate: | 200/Always OK, Worst: 200
|
| [C8] Write/Multi-Zone Error Rate: | 100/Always OK, Worst: 253
|
| [F0] Head Flying Hours: | 98/Always OK, Worst: 98 (Data = 2005,0)
|
| [F1] Lifetime Writes from Host (LBAs Written): | 200/Always OK, Worst: 200 (Data = 4014819621,1)
|
| [F2] Lifetime Reads from Host (LBAs Read): | 200/Always OK, Worst: 200 (Data = 518110108,1)
|
| [FE] Free Fall Protection: | 200/Always OK, Worst: 200
|