| |
|
| [General Information]
|
| Processor Name: | Mobile AMD Athlon XP 2000+
|
| Current Processor Frequency: | 1525.8 MHz
|
| Current Processor Frequency [MHz]: | 1526
|
| | |
|
| CPU ID: | 000006A0
|
| Extended CPU ID: | 000007A0
|
| CPU Brand Name: | mobile AMD Athlon(tm) XP-M (LV) 2000+
|
| CPU Vendor: | AuthenticAMD
|
| CPU Stepping: | A2
|
| CPU Code Name: | Barton
|
| CPU Technology: | 130 nm
|
| CPU Platform: | Socket A (462)
|
| | |
|
| Number of CPU Cores: | 1
|
| Number of Logical CPUs: | 1
|
| | |
|
| [Operating Points]
|
| CPU Current: | 1525.8 MHz = 11.50 x 132.7 MHz
|
| | |
|
| CPU Bus Type: | FSB (DDR)
|
| | |
|
| [Cache and TLB]
|
| L1 Cache: | Instruction: 64 KBytes, Data: 64 KBytes
|
| L2 Cache: | Integrated: 512 KBytes
|
| Instruction TLB: | Fully associative, 16 entries
|
| Data TLB: | Fully associative, 32 entries
|
| | |
|
| [Standard Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| Pentium-style Model Specific Registers | Present
|
| Physical Address Extension | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip / PGE (AMD) | Not Present
|
| Fast System Call | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Processor Number | Not Present
|
| CLFLUSH Instruction | Not Present
|
| Debug Trace and EMON Store | Not Present
|
| Internal ACPI Support | Not Present
|
| MMX Technology | Present
|
| Fast FP Save/Restore (IA MMX-2) | Present
|
| Streaming SIMD Extensions | Present
|
| Streaming SIMD Extensions 2 | Not Present
|
| Self-Snoop | Not Present
|
| Multi-Threading Capable | Not Present
|
| Automatic Clock Control | Not Present
|
| IA-64 Processor | Not Present
|
| Signal Break on FERR | Not Present
|
| Streaming SIMD Extensions 3 | Not Present
|
| PCLMULQDQ Instruction Support | Not Present
|
| MONITOR/MWAIT Support | Not Present
|
| Supplemental Streaming SIMD Extensions 3 | Not Present
|
| FMA Extension | Not Present
|
| CMPXCHG16B Support | Not Present
|
| Streaming SIMD Extensions 4.1 | Not Present
|
| Streaming SIMD Extensions 4.2 | Not Present
|
| x2APIC | Not Present
|
| POPCNT Instruction | Not Present
|
| AES Cryptography Support | Not Present
|
| XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Not Present
|
| XGETBV/XSETBV OS Enabled | Not Present
|
| AVX Support | Not Present
|
| Half-Precision Convert (CVT16) | Not Present
|
| [Extended Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| AMD-style Model Specific Registers | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip | Not Present
|
| SYSCALL and SYSRET Instructions | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Multi-Processing / Brand feature | Present
|
| No Execute | Not Present
|
| MMX Technology | Present
|
| MMX+ Extensions | Present
|
| Fast FP Save/Restore | Present
|
| Fast FP Save/Restore Optimizations | Not Present
|
| 1 GB large page support | Not Present
|
| RDTSCP Instruction | Not Present
|
| x86-64 Long Mode | Not Present
|
| 3DNow! Technology Extensions | Present
|
| 3DNow! Technology | Present
|
| LAHF/SAHF Long Mode Support | Not Present
|
| Core Multi-Processing Legacy Mode | Not Present
|
| Secure Virtual Machine | Not Present
|
| Extended APIC Register Space | Not Present
|
| LOCK MOV CR0 Support | Not Present
|
| Advanced Bit Manipulation | Not Present
|
| SSE4A Support | Not Present
|
| Misaligned SSE Mode | Not Present
|
| PREFETCH(W) Support | Not Present
|
| OS Visible Work-around Support | Not Present
|
| Instruction Based Sampling | Not Present
|
| XOP Instruction Support | Not Present
|
| SKINIT, STGI, and DEV Support | Not Present
|
| Watchdog Timer Support | Not Present
|
| TBM0 Instruction Support | Not Present
|
| Lightweight Profiling Support | Not Present
|
| FMA4 Instruction Support | Not Present
|
| Translation Cache Extension | Not Present
|
| NodeId Support | Not Present
|
| Trailing Bit Manipulation | Not Present
|
| Topology Extensions | Not Present
|
| Core Performance Counter Extensions | Not Present
|
| NB Performance Counter Extensions | Not Present
|
| Streaming Performance Monitor Architecture | Not Present
|
| Data Breakpoint Extension | Not Present
|
| Performance Time-Stamp Counter | Not Present
|
| L2I Performance Counter Extensions | Not Present
|
| MWAITX/MONITORX Support | Not Present
|
| Secure Memory Encryption | Not Present
|
| Secure Encrypted Virtualization | Not Present
|
| | |
|
| [Enhanced Features]
|
| Core Performance Boost | Not Supported
|
| | |
|
| [Memory Ranges]
|
| Maximum Physical Address Size: | 34-bit (16 GBytes)
|
| Maximum Virtual Address Size: | 32-bit (4 GBytes)
|
| [MTRRs]
|
| Range 0-40000000 (0MB-1024MB) Type: | Write Back (WB)
|
| Range 3E000000-40000000 (992MB-1024MB) Type: | Uncacheable (UC)
|
| Range D8000000-D8200000 (3456MB-3458MB) Type: | Write Combining (WC)
|
| |
|
| [General Information]
|
| Device Name: | VIA VT8233A CF/VT8235 PCI-to-ISA Bridge
|
| Original Device Name: | VIA VT8233A CF/VT8235 PCI-to-ISA Bridge
|
| Device Class: | PCI-to-ISA Bridge
|
| Revision ID: | 0
|
| PCI Address (Bus:Device:Function) Number: | 0:17:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1106&DEV_3177&SUBSYS_00001106&REV_00
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | (Standard system devices)
|
| Driver Description: | PCI standard ISA bridge
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_3177&SUBSYS_00000000&REV_00\3&a mp;61AAA01&0&88
|
| | |
|
| [ISA Bus Control]
|
| ISA Command Delay: | Normal
|
| I/O Recovery Time: | Enabled
|
| ROM Wait States: | 1 WS
|
| ROM Write: | Disabled
|
| Double DMA Clock: | 4 MHz
|
| 4D0/4D1 Port Configuration: | Enabled
|
| DMA/Interrupt/Timer Shadow Register Read: | Disabled
|
| Double ISA Bus Clock: | PCLK/4 = 8 MHz
|
| | |
|
| [BIOS ROM Decode Control]
|
| FFF00000h-FFF7FFFFh: | Disabled
|
| FFE80000h-FFEFFFFFh: | Disabled
|
| FFE00000h-FFE7FFFFh: | Disabled
|
| FFD80000h-FFDFFFFFh: | Disabled
|
| FFD00000h-FFD7FFFFh: | Disabled
|
| FFC80000h-FFCFFFFFh: | Disabled
|
| FFC00000h-FFC7FFFFh: | Disabled
|
| | |
|
| [Line Buffer Control]
|
| ISA Master DMA Line Buffer: | Enabled
|
| Gate Interrupt Until Line Buffer Flush Complete: | Enabled
|
| Flush Line Buffer for Interrupt: | Enabled
|
| Uninterruptable Burst Read: | Enabled
|
| Gate IRQ Until Line Bufer Flush Completed: | Enabled
|
| | |
|
| [Delay Transaction Control]
|
| Delayed Transactions (PCI 2.1): | Enabled
|
| Only Posted Write: | Disabled
|
| Write Delay Transaction Timeout Timer: | Enabled
|
| Read Delay Transaction Timeout Timer: | Enabled
|
| | |
|
| [Read Pass Write Control]
|
| APIC FSB Fixed at Low DW: | Disabled
|
| AC97 / LPC Read Pass Write: | Enabled
|
| IDE Read Pass Write: | Enabled
|
| USB Read Pass Write: | Disabled
|
| NIC Read Pass Write: | Disabled
|
| | |
|
| [CCA Control]
|
| South Bridge Internal Master Devices Priority Higher Than External PCI Master: | Disabled
|
| CCA Clean to Mask Off IRQ: | Enabled
|
| WSC Mask Off INTR: | Disabled
|
| | |
|
| [IDE Interrupt Routing]
|
| I/O Recovery Time: | 2 BCLKs
|
| Secondary IDE Channel IRQ Routing: | IRQ15
|
| Primary IDE Channel IRQ Routing: | IRQ14
|
| | |
|
| [Function Control 1]
|
| MC'97 Controller: | Enabled
|
| AC'97 Controller: | Enabled
|
| USB 1.1 UHCI Ports 2-3: | Enabled
|
| USB 1.1 UHCI Ports 0-1: | Enabled
|
| IDE Controller: | Enabled
|
| USB 1.1 UHCI Ports 4-5: | Enabled
|
| USB 2.0 EHCI: | Enabled
|
| Internal Audio: | Enabled
|
| | |
|
| [Function Control 2]
|
| Internal LAN Controller Clock Gating: | Disabled
|
| Internal LAN Controller: | Enabled
|
| Internal RTC: | Enabled
|
| Internal PS/2 Mouse: | Disabled
|
| Internal KBC Configuration: | Disabled
|
| Internal KBC: | Disabled
|
| | |
|
| [Serial IRQ & LPC Control]
|
| LPC Short Wait Abort: | Disabled
|
| LPC Frame Wait State Time: | 1 T
|
| LPC Stop to Start Frame Wait State: | Enabled
|
| Serial IRQ: | Enabled
|
| Serial IRQ Mode: | Continuous
|
| Serial IRQ Start-Frame Width: | 4 PCICLKs
|
| | |
|
| [PC/PCI DMA Control]
|
| PCI DMA Pair A and B: | Disabled
|
| PCI DMA Channel 7: | Disabled
|
| PCI DMA Channel 6: | Disabled
|
| PCI DMA Channel 5: | Disabled
|
| PCI DMA Channel 3: | Disabled
|
| PCI DMA Channel 2: | Disabled
|
| PCI DMA Channel 1: | Disabled
|
| PCI DMA Channel 0: | Disabled
|
| | |
|
| [PCI Interrupt Polarity]
|
| PCI INTA#: | Level-sensitive
|
| PCI INTB#: | Level-sensitive
|
| PCI INTC#: | Level-sensitive
|
| PCI INTD#: | Level-sensitive
|
| | |
|
| [PCI PNP Interrupt Routing 1]
|
| PCI INTA# Routing: | IRQ11
|
| | |
|
| [PCI PNP Interrupt Routing 2]
|
| PCI INTC# Routing: | IRQ10
|
| PCI INTB# Routing: | IRQ3
|
| | |
|
| [PCI PNP Interrupt Routing 3]
|
| PCI INTD# Routing: | IRQ6
|
| | |
|
| [Miscellaneous Control 0]
|
| Internal APIC: | Disabled
|
| South Bridge Interrupt Cycles Run at 33 MHz: | Disabled
|
| Address Decode: | Subtractive
|
| RTC High Bank Access: | Disabled
|
| RTC Rx32 Write Protect: | Disabled
|
| RTC Rx0D Write Protect: | Enabled
|
| RTC Rx32 Map to Century Byte: | Disabled
|
| | |
|
| [Miscellaneous Control 1]
|
| LPC RTC: | Disabled
|
| LPC Keyboard: | Enabled
|
| External MCCS to LPC: | Enabled
|
| Internal MCCS: | Enabled
|
| A20M# Active: | Disabled
|
| NMI on PCI Parity Error: | Disabled
|
| | |
|
| [DMA Bandwidth Control]
|
| DMA Channel 7 Bandwidth: | Improved
|
| DMA Channel 6 Bandwidth: | Improved
|
| DMA Channel 5 Bandwidth: | Improved
|
| DMA Single Transfer Mode Bandwidth: | Improved
|
| DMA Channel 3 Bandwidth: | Improved
|
| DMA Channel 2 Bandwidth: | Improved
|
| DMA Channel 1 Bandwidth: | Improved
|
| DMA Channel 0 Bandwidth: | Improved
|
| | |
|
| [Miscellaneous Control 2]
|
| Bypass APIC De-Assert Message: | Disabled
|
| APIC LDT Mode: | Disabled
|
| INTE#, INTF#, INTG#, INTH#: | Disabled
|
| Dynamic Clock Stop: | Enabled
|
| | |
|
| [PCS Control]
|
| PCS 0 I/O Port Address: | 0
|
| PCS 1 I/O Port Address: | 804
|
| PCS 2 I/O Port Address: | 0
|
| PCS 3 I/O Port Address: | 0
|
| | |
|
| [PCS I/O Port Address Mask]
|
| PCS 3 I/O Port Address Mask (Range): | 1 Byte
|
| PCS 2 I/O Port Address Mask (Range): | 1 Byte
|
| PCS 1 I/O Port Address Mask (Range): | 2 Bytes
|
| PCS 0 I/O Port Address Mask (Range): | 1 Byte
|
| | |
|
| [PCS Control]
|
| PCS 3 Internal I/O: | Disabled
|
| PCS 2 Internal I/O: | Disabled
|
| PCS 1 Internal I/O: | Disabled
|
| PCS 0 Internal I/O: | Disabled
|
| PCS 3: | Disabled
|
| PCS 2: | Disabled
|
| PCS 1: | Enabled
|
| PCS 0: | Disabled
|
| | |
|
| [Output Control]
|
| FERR Voltage: | 1.5 V
|
| | |
|
| [ISA Positive Decoding Control 1]
|
| On-Board I/O Port Positive Decoding: | Disabled
|
| MSS I/O Port Positive Decoding: | Disabled
|
| MSS I/O Decode Range: | 0530h-0537h
|
| Internal APIC Positive Decoding: | Disabled
|
| BIOS ROM Positive Decoding: | Disabled
|
| Internal PCS1# Positive Decoding: | Disabled
|
| Internal PCS0# Positive Decoding: | Disabled
|
| | |
|
| [ISA Positive Decoding Control 2]
|
| FDC Positive Decoding: | Disabled
|
| LPT Positive Decoding: | Disabled
|
| LPT Decode Range: | 3BCh-3BFh, 7BCh-7BEh
|
| Game Port Positive Decoding: | Disabled
|
| MIDI Positive Decoding: | Disabled
|
| MIDI Decode Range: | 300h-303h
|
| | |
|
| [ISA Positive Decoding Control 3]
|
| COM Port B Positive Decoding: | Disabled
|
| COM Port B Decode Range: | 3F8h-3FFh
|
| COM Port A Positive Decoding: | Disabled
|
| COM Port A Decode Range: | 3F8h-3FFh
|
| | |
|
| [ISA Positive Decoding Control 4]
|
| PCS2# and PCS3# Positive Decoding: | Disabled
|
| I/O Port 0CF9h Positive Decoding: | Disabled
|
| FDC Decoding Range: | Primary
|
| Sound Blaster Positive Decoding: | Disabled
|
| Sound Blaster Decode Range: | 220h-233h
|
| | |
|
| [I/O Pad Control]
|
| IDE Interface Output Drive Strength: | 2
|
| PLL PCLK Input Delay Select: | 0
|
| PLL CLK66 Feedback Delay Select: | 0
|
| | |
|
| [General Configuration 0]
|
| Sleep Button: | Disabled
|
| Debounce LID and PWRBTN# Inputs for 200us: | Enabled
|
| Microsoft Sound Monitor in Audio Access: | Disabled
|
| Game Port Monitor in Audio Access: | Disabled
|
| Sound Blaster Monitor in Audio Access: | Disabled
|
| MIDI Monitor in Audio Access: | Disabled
|
| | |
|
| [General Configuration 1]
|
| I/O Enable for ACPI I/O Base: | Enabled
|
| ACPI Timer Count Select: | 24-bit
|
| RTC Enable Signal Gated with PSON (SUSC#) in Soft-Off Mode: | Enabled
|
| Clock Throttling Clock Select (STPCLK#): | 30 (480) usec
|
| | |
|
| [ACPI Interrupt Select]
|
| ATX / AT Power Indicator: | ATX
|
| SUSC# State: | 1
|
| SUSC# AC-Power-On Default Value: | 0
|
| SCI Interrupt Assignment: | IRQ9
|
| | |
|
| [Primary Interrupt Channel]
|
| IRQ15 As Pri. Int. Channel: | Disabled
|
| IRQ14 As Pri. Int. Channel: | Disabled
|
| IRQ13 As Pri. Int. Channel: | Disabled
|
| IRQ12 As Pri. Int. Channel: | Enabled
|
| IRQ11 As Pri. Int. Channel: | Disabled
|
| IRQ10 As Pri. Int. Channel: | Disabled
|
| IRQ9 As Pri. Int. Channel: | Disabled
|
| IRQ8 As Pri. Int. Channel: | Disabled
|
| IRQ7 As Pri. Int. Channel: | Disabled
|
| IRQ6 As Pri. Int. Channel: | Disabled
|
| IRQ5 As Pri. Int. Channel: | Disabled
|
| IRQ4 As Pri. Int. Channel: | Disabled
|
| IRQ3 As Pri. Int. Channel: | Disabled
|
| IRQ1 As Pri. Int. Channel: | Enabled
|
| IRQ0 As Pri. Int. Channel: | Disabled
|
| | |
|
| [Secondary Interrupt Channel]
|
| IRQ15 As Sec. Int. Channel: | Disabled
|
| IRQ14 As Sec. Int. Channel: | Disabled
|
| IRQ13 As Sec. Int. Channel: | Disabled
|
| IRQ12 As Sec. Int. Channel: | Disabled
|
| IRQ11 As Sec. Int. Channel: | Disabled
|
| IRQ10 As Sec. Int. Channel: | Disabled
|
| IRQ9 As Sec. Int. Channel: | Disabled
|
| IRQ8 As Sec. Int. Channel: | Disabled
|
| IRQ7 As Sec. Int. Channel: | Disabled
|
| IRQ6 As Sec. Int. Channel: | Disabled
|
| IRQ5 As Sec. Int. Channel: | Disabled
|
| IRQ4 As Sec. Int. Channel: | Disabled
|
| IRQ3 As Sec. Int. Channel: | Disabled
|
| IRQ1 As Sec. Int. Channel: | Disabled
|
| IRQ0 As Sec. Int. Channel: | Disabled
|
| | |
|
| [Power Management I/O Base]
|
| PM I/O Register Base Address: | 800
|
| | |
|
| [Host Bus Power Management Control]
|
| Thermal Duty Cycle: |
|
| THRM: | Disabled
|
| Processor Break Event: | Disabled
|
| | |
|
| [Throttle / Clock Stop Control]
|
| Throttle Timer: | 4-Bit
|
| Fast Clock (7.5us) as Throttle Timer Tick: | Enabled
|
| SMI Level Output (Low): | Enabled
|
| Internal Clock Stop for PCI Idle: | Disabled
|
| Internal Clock Stop During C3: | Disabled
|
| Internal Clock Stop During Suspend: | Disabled
|
| | |
|
| [GP Timer Control]
|
| Conserve Mode Timer Count Value: | 1/16 sec
|
| System In Power-Conservation Mode: | No
|
| Power-Conservation Mode: | Disabled
|
| Secondary Event Timer Count Value: | 2 ms
|
| Secondary Event: | Not occurred
|
| Secondary Event Timer: | Disabled
|
| GP1 Timer Count: | 8
|
| GP0 Timer Count: | 4
|
| GP1 Timer: | Not Started
|
| GP1 Timer Automatic Reload: | Disabled
|
| GP1 Timer Base: | Disabled
|
| GP0 Timer: | Not Started
|
| GP0 Timer Automatic Reload: | Disabled
|
| GP0 Timer Base: | Disabled
|
| | |
|
| [Power Well Control]
|
| SMBus Clock Select: | From RTC 32.768 kHz
|
| Internal PLL Reset During Suspend: | Disabled
|
| SUSST1# / GPO3 Select: | GPO3
|
| GPO2 / SUSB# Select: | SUSB#
|
| GPO1 / SUSA# Select: | SUSA#
|
| GPO0 Output Select: | Fixed Output Level
|
| | |
|
| [Miscellaneous Power Well Control]
|
| CPUSTP# to SUSST# Delay Select: | 125 usec min.
|
| SUSST# Deasserted Before PWRGD for STD: | Enabled
|
| Keyboard / Mouse Port Swap: | Disabled
|
| SMB2 / GPO Select: | SMBDT2 / SMBCK2
|
| AOL 2 SMB Slave: | Disabled
|
| SUSCLK / GPO4 Select: | SUSCLK
|
| USB Wakeup for STR / STD / SoftOff: | Enabled
|
| | |
|
| [Power On / Reset Control]
|
| CPU Frequency Strapping Value Output to NMI, INTR, IGNNE#, and A20M# during RESET#: | C
|
| | |
|
| [GP2/GP3 Timer Control]
|
| GP3 Timer: | Not Started
|
| GP3 Timer Automatic Reload: | Disabled
|
| GP3 Timer Tick Select: | 1/16 sec
|
| GP2 Timer: | Not Started
|
| GP2 Timer Automatic Reload: | Disabled
|
| GP2 Timer Tick Select: | Disabled
|
| | |
|
| [GP2 Timer]
|
| GP2 Timer Current Count: | 137
|
| | |
|
| [GP3 Timer]
|
| GP3 Timer Current Count: | 0
|
| | |
|
| [SMBus I/O Base]
|
| SMBus I/O Base Address: | 400
|
| | |
|
| [SMBus Host Configuration]
|
| SMBus Interrupt Type: | SMI
|
| SMBus Interrupt: | Disabled
|
| SMBus Host Controller: | Enabled
|
| | |
|
| [SMBus Slave Address for Port 1]
|
| SMBus Slave Address for Port 1: | 0
|
| R/W for Shadow Port 1: | Disabled
|
| | |
|
| [SMBus Slave Address for Port 2]
|
| SMBus Slave Address for Port 2: | 0
|
| R/W for Shadow Port 2: | Disabled
|
| | |
|
| [SMBus Revision ID]
|
| SMBus Revision ID: | 0
|
| | |
|
| [GPI Inversion Control]
|
| GPI27 Input: | Non-inverted
|
| GPI26 Input: | Non-inverted
|
| GPI25 Input: | Non-inverted
|
| GPI24 Input: | Non-inverted
|
| GPI19 Input: | Non-inverted
|
| GPI18 Input: | Non-inverted
|
| GPI17 Input: | Non-inverted
|
| GPI16 Input: | Non-inverted
|
| | |
|
| [GPI SCI/SMI Select]
|
| GPI27 Interrupt: | SCI
|
| GPI26 Interrupt: | SCI
|
| GPI25 Interrupt: | SCI
|
| GPI24 Interrupt: | SCI
|
| GPI19 Interrupt: | SCI
|
| GPI18 Interrupt: | SCI
|
| GPI17 Interrupt: | SCI
|
| GPI16 Interrupt: | SCI
|
| | |
|
| [GPO Pin Select]
|
| ACSDIN2,3 / GPIO20,21 Select: | ACSDIN2 / ACSDIN3
|
| SA[19:16] / GPO[19:16] Select: | SA[19:16]
|
| GPIO[15:12] Direction: | Input
|
| GPIO[11:8] Direction: | Input
|
| GNT5#/GPO7, REQ5#/GPI7 Select: | GNT5#, REQ5#
|
| PCISTP#/GPO6 Select: | PCISTP#
|
| CPUSTP#/GPO5 Select: | CPUSTP#
|
| | |
|
| [GPIO I/O Select 1]
|
| Voltage Regulator Change Timer Select: | 100 usec
|
| AGPBZ# Source of Bus Master Status: | Disabled
|
| VGATE on GPIO8: | GPIO8
|
| CPU Frequency Change: | Enabled
|
| PCS1# on ACSDIN3: | PCS1#
|
| PCS0# on ACSDIN2: | PCS0#
|
| IORDY/GPI19 Select: | GPI19
|
| | |
|
| [GPIO I/O Select 2]
|
| GPI31/GPO31 (GPIOE) Select: | GPI31
|
| GPI30/GPO30 (GPIOD) Select: | GPI30
|
| GPI25/GPO25 (GPIOC) Select: | GPI25
|
| GPI24/GPO24 (GPIOA) Select: | GPO24/GPIOA
|
| | |
|
| [GPO Output Type]
|
| GPO31 Output Type: | OD
|
| GPO30 Output Type: | OD
|
| GPO25 Output Type: | OD
|
| GPO24 Output Type: | TTL
|
| |
|
| [General Information]
|
| Device Name: | VIA VT82C571 Integrated IDE Controller
|
| Original Device Name: | VIA VT82C571 Integrated IDE Controller
|
| Device Class: | IDE Controller
|
| Revision ID: | 6
|
| PCI Address (Bus:Device:Function) Number: | 0:17:1
|
| PCI Latency Timer: | 32
|
| Hardware ID: | PCI\VEN_1106&DEV_0571&SUBSYS_120514FF&REV_06
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | INTA#
|
| I/O Base Address 4 | FC00
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | VIA Technologies, Inc.
|
| Driver Description: | VIA Bus Master IDE Controller
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_0571&SUBSYS_120514FF&REV_06\3&a mp;61AAA01&0&89
|
| | |
|
| [Chip Enable]
|
| Primary IDE Channel: | Enabled
|
| Secondary IDE Channel: | Enabled
|
| | |
|
| [IDE Configuration I]
|
| Primary IDE Read Prefetch Buffer: | Enabled
|
| Primary IDE Post Write Buffer: | Enabled
|
| Secondary IDE Read Prefetch Buffer: | Enabled
|
| Secondary IDE Post Write Buffer: | Enabled
|
| | |
|
| [IDE Configuration II]
|
| PIO Operating Mode - Primary Channel: | Compatibility Mode
|
| PIO Operating Mode - Secondary Channel: | Compatibility Mode
|
| | |
|
| [FIFO Configuration]
|
| FIFO Configuration: | PRI = 16, SEC = 0
|
| Primary Channel FIFO Threshold: | 1/2
|
| Secondary Channel FIFO Threshold: | 1/2
|
| | |
|
| [Miscellaneous Control 1]
|
| Master Read Cycle IRDY# Wait State: | 0 WS
|
| Master Write Cycle IRDY# Wait State: | 0 WS
|
| FIFO Output Data 1/2 Clock Advance/PIO Read Pre-Fetch Byte Counter: | Enabled
|
| Bus-Master IDE Status Register Read Retry: | Enabled
|
| Packet Command Prefetching: | Disabled
|
| UltraDMA Host Must Wait for First Transfer Before Termination: | Enabled
|
| | |
|
| [Miscellaneous Control 2]
|
| Interrupt Steering Swap Between Channels: | Disabled
|
| Rx3C Write Protect: | Enabled
|
| Memory-Read-Multiple Command: | Enabled
|
| Memory-Write-and-Invalidate Command: | Enabled
|
| | |
|
| [Miscellaneous Control 3]
|
| Read DMA FIFO Flush (PRI): | Enabled
|
| Read DMA FIFO Flush (SEC): | Enabled
|
| End-of-Sector FIFO Flush (PRI): | Disabled
|
| End-of-Sector FIFO Flush (SEC): | Disabled
|
| Maximum DRDY# Pulse Width: | Unlimited
|
| | |
|
| [Drive Timing Control]
|
| Primary Drive 0 Active Pulse Width: | 3 clocks
|
| Primary Drive 0 Recovery Time: | 1 PCICLKs
|
| Primary Drive 1 Active Pulse Width: | 2 PCICLKs
|
| Primary Drive 1 Recovery Time: | 2 clocks
|
| Secondary Drive 0 Active Pulse Width: | 3 clocks
|
| Secondary Drive 0 Recovery Time: | 1 PCICLKs
|
| Secondary Drive 1 Active Pulse Width: | 2 PCICLKs
|
| Secondary Drive 1 Recovery Time: | 2 clocks
|
| | |
|
| [Address Setup Time]
|
| Primary Drive 0 Address Setup Time: | 4T
|
| Primary Drive 1 Address Setup Time: | 4T
|
| Secondary Drive 0 Address Setup Time: | 4T
|
| Secondary Drive 1 Address Setup Time: | 4T
|
| | |
|
| [Secondary Non-01F0h Port Access Timing]
|
| DIOR#/DIOW# Active Pulse Width: | 12 PCICLKs
|
| DIOR#/DIOW# Recovery Time: | 7 PCICLKs
|
| | |
|
| [Primary Non-01F0h Port Access Timing]
|
| DIOR#/DIOW# Active Pulse Width: | 12 PCICLKs
|
| DIOR#/DIOW# Recovery Time: | 7 PCICLKs
|
| | |
|
| [Ultra-DMA Extended Timing Control (SEC DRV 1)]
|
| Ultra-DMA Mode Enable Method: | Using Set Feature Cmd.
|
| Ultra-DMA Mode: | Disabled
|
| Transfer Mode: | DMA or PIO
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 9T
|
| | |
|
| [Ultra-DMA Extended Timing Control (SEC DRV 0)]
|
| Ultra-DMA Mode Enable Method: | Using this reg.
|
| Ultra-DMA Mode: | Enabled
|
| Transfer Mode: | Ultra-DMA
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 8T
|
| | |
|
| [Ultra-DMA Extended Timing Control (PRI DRV 1)]
|
| Ultra-DMA Mode Enable Method: | Using Set Feature Cmd.
|
| Ultra-DMA Mode: | Disabled
|
| Transfer Mode: | DMA or PIO
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 9T
|
| | |
|
| [Ultra-DMA Extended Timing Control (PRI DRV 0)]
|
| Ultra-DMA Mode Enable Method: | Using this reg.
|
| Ultra-DMA Mode: | Enabled
|
| Transfer Mode: | Ultra-DMA
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 3T
|
| | |
|
| [Ultra-DMA FIFO Control]
|
| Lower ISA Request Priority When Write Device Packet Command is Issued: | Disabled
|
| Clear Native Mode Interrupt on Falling Edge of Gated Interrupt: | Disabled
|
| Improve PIO Prefetch and Post-Write Performance: | Enabled
|
| Memory Prefetch Size: | 2 lines
|
| Change Drive Clears All FIFO & Internal States: | Enabled
|
| Complete DMA Cycle with Transfer Size Less Than FIFO Size: | Enabled
|
| | |
|
| [IDE Clock Gating]
|
| Dynamic 100/133 MHz Clock Gating: | Enabled
|
| Dynamic 66 MHz Clock Gating: | Enabled
|
| | |
|
| [Primary Sector Size]
|
| Sector Size: | 512 Bytes/Sector
|
| | |
|
| [Secondary Sector Size]
|
| Sector Size: | 512 Bytes/Sector
|
| |
|
| [General Information]
|
| Drive Controller: | E-IDE (ATA-6)
|
| Host Controller: | Primary IDE Channel
|
| Drive Channel: | Primary, Master
|
| Drive Model: | Hitachi IC25N040ATMR04-0
|
| Drive Firmware Revision: | MO2OAD4A
|
| Drive Serial Number: | MRG208KBH8H7ZH
|
| Drive Capacity: | 38,154 MBytes (40 GB)
|
| Drive Capacity [MB]: | 38154
|
| ATA Major Version Supported: | ATA/ATAPI-5, ATA/ATAPI-6
|
| ATA Minor Version Supported: | ATA/ATAPI-6 T13 1410D version 3a
|
| | |
|
| [Drive Geometry]
|
| Number of Cylinders: | 16383
|
| Number of Heads: | 16
|
| Sectors Per Track: | 63
|
| Number Of ECC Bytes: | 4
|
| Number of Sectors: | 16514064
|
| Total 32-bit LBA Sectors: | 78140160
|
| Total 48-bit LBA Sectors: | 78140160
|
| Logical Sector Size: | 512 Bytes
|
| Cache Buffer Size: | 1740 KBytes
|
| Controller Type: | Dual Ported, Multiple Sector Buffer, Read Cache
|
| | |
|
| [Transfer Modes]
|
| Sectors Per Interrupt: | Total: 16, Active: 16
|
| Max. PIO Transfer Mode: | 4
|
| Multiword DMA Mode: | Total: 2, Active: -
|
| Singleword DMA Mode: | Total: -, Active: -
|
| Ultra-DMA Mode: | Total: 5 (ATA-100), Active: 5 (ATA-100)
|
| Max. Multiword DMA Transfer Rate: | 16.7 MBytes/s
|
| Max. PIO with IORDY Transfer Rate: | 8.3 MBytes/s
|
| Max. PIO w/o IORDY Transfer Rate: | 16.7 MBytes/s
|
| Transfer Width: | 16-bit
|
| Native Command Queuing: | Not Supported
|
| TRIM Command: | Not Supported
|
| | |
|
| [Device flags]
|
| Fixed Drive: | Present
|
| Removable Drive: | Not Present
|
| Magnetic Storage: | Present
|
| LBA Mode: | Supported
|
| DMA Mode: | Supported
|
| IORDY: | Supported
|
| IORDY Disableable: | Supported
|
| | |
|
| [Features]
|
| Write Cache: | Present, Active
|
| S.M.A.R.T. Feature: | Present, Active
|
| Security Feature: | Present, Inactive
|
| Removable Media Feature: | Not Present, Disabled
|
| Power Management: | Present, Active
|
| Advanced Power Management: | Present, Active
|
| Packet Interface: | Not Present, Disabled
|
| Look-Ahead Buffer: | Present, Active
|
| Host Protected Area: | Present, Enabled
|
| Power-Up In Standby: | Supported, Inactive
|
| Automatic Acoustic Management: | Supported, Inactive
|
| 48-bit LBA: | Supported, Active
|
| Host-Initiated Link Power Management (HIPM): | Not Supported
|
| Device-Initiated Link Power Management (DIPM): | Not Supported
|
| In-Order Data Delivery: | Not Supported
|
| Hardware Feature Control: | Not Supported
|
| Software Settings Preservation: | Not Supported
|
| NCQ Autosense: | Not Supported
|
| Link Power State Device Sleep: | Not Supported
|
| Hybrid Information Feature: | Not Supported
|
| Rebuild Assist: | Not Supported
|
| Power Disable: | Not Supported
|
| All Write Cache Non-Volatile: | Not Supported
|
| Extended Number of User Addressable Sectors: | Not Supported
|
| CFast Specification: | Not Supported
|
| NCQ Priority Information: | Not Supported
|
| Host Automatic Partial to Slumber Transitions: | Not Supported
|
| Device Automatic Partial to Slumber Transitions: | Not Supported
|
| NCQ Streaming: | Not Supported
|
| NCQ Queue Management Command: | Not Supported
|
| DevSleep to Reduced Power State: | Not Supported
|
| Out Of Band Management Interface: | Not Supported
|
| | |
|
| [Security]
|
| Security Feature: | Supported
|
| Security Status: | Disabled
|
| Security Locked: | Disabled
|
| Security Frozen: | Enabled
|
| Enhanced Security Erase: | Not Supported
|
| Sanitize Feature: | Not Supported
|
| Sanitize Device - Crypto Scramble: | Not Supported
|
| Sanitize Device - Overwrite: | Not Supported
|
| Sanitize Device - Block Erase: | Not Supported
|
| Sanitize Device - Antifreeze Lock: | Not Supported
|
| Device Encrypts All User Data: | Not Supported
|
| Trusted Computing: | Not Supported
|
| | |
|
| [Self-Monitoring, Analysis and Reporting Technology (S.M.A.R.T.)]
|
| [01] Raw Read Error Rate: | 100/62, Worst: 100
|
| [02] Throughput Performance: | 100/40, Worst: 100
|
| [03] Spin Up Time: | 175/33, Worst: 175 (Data = 1,13)
|
| [04] Start/Stop Count: | 99/Always OK, Worst: 99 (Data = 1722,0)
|
| [05] Reallocated Sector Count: | 100/5, Worst: 100
|
| [07] Seek Error Rate: | 100/67, Worst: 100
|
| [08] Seek Time Performance: | 100/40, Worst: 100
|
| [09] Power-on Hours/Cycle Count: | 97/Always OK, Worst: 97 (1533 hours / 63.9 days)
|
| [0A] Spin Retry Count: | 100/60, Worst: 100
|
| [0C] Power Cycle Count: | 99/Always OK, Worst: 99 (Data = 1655,0)
|
| [BF] G-Sense Error Rate: | 100/Always OK, Worst: 100 (Data = 65536,0)
|
| [C0] Power-Off Retract Count: | 100/Always OK, Worst: 100 (Data = 59,0)
|
| [C1] Load/Unload Cycle Count: | 98/Always OK, Worst: 98 (Data = 26426,0)
|
| [C2] Temperature: | 141/Always OK, Worst: 141 (39.0 °C)
|
| [C4] Reallocation Event Count: | 100/Always OK, Worst: 100 (Data = 6,0)
|
| [C5] Current Pending Sector Count: | 100/Always OK, Worst: 100
|
| [C6] Off-Line Uncorrectable Sector Count: | 100/Always OK, Worst: 100
|
| [C7] UltraDMA/SATA CRC Error Rate: | 200/Always OK, Worst: 200
|
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