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fpga 6502 [message #209778] Wed, 01 May 2013 17:28 Go to next message
christianlott1 is currently offline  christianlott1
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http://visual6502.org/wiki/index.php?title=6502_-_simulating _in_real_time_on_an_FPGA

So I've got this info about the simulations done 2 years ago.

I'm wondering if any product is forth coming other than the

http://www.mirifica.it/store/lang-en/66-oho-elektronik-godil 40xc3s250e.html


I'm wondering because that product itself is amazing enough but if
there were attached:

1: a way to wireless access the fpga (like pause, download new info,
etc)

2: piggy back the original 6510 between the fpga and main board.

As in (2), using the original 6510 as the main ensures compatibility
while having the fpga able to pause the processor, retrieve registers,
directly download to memory, record address access, etc would act like
an in circuit emulator.

$80 US is a pretty high price considering other tiny fpga products
like the Xula:

https://xess.com/prods/prod055.php

but achieves further since the xula is not set up for the 5v <-> 3v
interaction.


Thanks.
Re: fpga 6502 [message #209839 is a reply to message #209778] Wed, 08 May 2013 10:47 Go to previous messageGo to next message
Groepaz is currently offline  Groepaz
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s1 wrote:

> http://visual6502.org/wiki/index.php?title=6502_-_simulating _in_real_time_on_an_FPGA
>
> So I've got this info about the simulations done 2 years ago.
>
> I'm wondering if any product is forth coming other than the
>
> http://www.mirifica.it/store/lang-en/66-oho-elektronik-godil 40xc3s250e.html
>
>
> I'm wondering because that product itself is amazing enough but if
> there were attached:
>
> 1: a way to wireless access the fpga (like pause, download new info,
> etc)
>
> 2: piggy back the original 6510 between the fpga and main board.
>
> As in (2), using the original 6510 as the main ensures compatibility
> while having the fpga able to pause the processor, retrieve registers,
> directly download to memory, record address access, etc would act like
> an in circuit emulator.

and then you notice it doesnt (and can not) work like this in a C64 for
various reasons. but it'd be great if it did, indeed :)

--

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Re: fpga 6502 [message #209841 is a reply to message #209839] Wed, 08 May 2013 19:23 Go to previous messageGo to next message
christianlott1 is currently offline  christianlott1
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> and then you notice it doesnt (and can not) work like this in a C64 for
> various reasons. but it'd be great if it did, indeed :)

which reasons? it says on that page that it emulated the 6510 from
netlist and from vhdl code. the netlist had problems emulating the
illegal ops for asic vs fpga analog reasons.
Re: fpga 6502 [message #209842 is a reply to message #209841] Thu, 09 May 2013 06:44 Go to previous messageGo to next message
Ingo Korb is currently offline  Ingo Korb
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s1 <christianlott1@yahoo.com> writes:

> which reasons? it says on that page that it emulated the 6510 from
> netlist and from vhdl code. the netlist had problems emulating the
> illegal ops for asic vs fpga analog reasons.

It also had timing problems - the FPGA ran the netlist evaluation at
approximately 50MHz and the synthesis tools output indicated that this
was the maximum this chip could do with this hardware description.

If you just want a 6510 FPGA replacement: Forget about using the 6502
net list and implement a high-level description of the 6502 plus the
6510 extras from scratch. It will be more compatible, easier to fix
problems if any show up and require less power and a smaller FPGA.

-ik
Re: fpga 6502 [message #209843 is a reply to message #209841] Thu, 09 May 2013 09:29 Go to previous messageGo to next message
Groepaz is currently offline  Groepaz
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s1 wrote:

>
>> and then you notice it doesnt (and can not) work like this in a C64 for
>> various reasons. but it'd be great if it did, indeed :)
>
> which reasons? it says on that page that it emulated the 6510 from
> netlist and from vhdl code. the netlist had problems emulating the
> illegal ops for asic vs fpga analog reasons.

emulating the 6502/10 is not the problem - its the other features you want.
eg it is not possible to "pause" the c64 by halting the cpu, the vic will
always continue running and doing its thing, and so will the cias - so its
not really a useful debug setup at all. (an emulator, such as vice, can do
this perfectly on the other hand)

--

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http://www.pokefinder.org http://ftp.pokefinder.org

Paranoide Innenminister sind der Pickel am Arsch der Demokratie
Re: fpga 6502 [message #209845 is a reply to message #209843] Thu, 09 May 2013 15:48 Go to previous messageGo to next message
christianlott1 is currently offline  christianlott1
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On May 9, 8:29 am, Groepaz <groe...@gmx.net> wrote:

> emulating the 6502/10 is not the problem - its the other features you want.
> eg it is not possible to "pause" the c64 by halting the cpu, the vic will
> always continue running and doing its thing, and so will the cias - so its
> not really a useful debug setup at all. (an emulator, such as vice, can do
> this perfectly on the other hand)

I see what you are saying. In this case, pausing the processor, you
would need to pause cia registers before you paused the processor with
a few sta $DDxx $DCxx to the timers beforehand. I don't see how the
vic would be hurt by the processors absence from the bus.

You are probably right in the end, I just don't understand the reasons
yet.

And since this chip already exists I guess that other stuff I
mentioned (wireless, piggy backed original) isn't necessary. The
effort wouldn't fit the demand/desire.

Thanks for responding.
Re: fpga 6502 [message #209846 is a reply to message #209842] Thu, 09 May 2013 17:46 Go to previous messageGo to next message
christianlott1 is currently offline  christianlott1
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On May 9, 5:44 am, Ingo Korb <use...@mail.snowcat.de> wrote:

> It also had timing problems - the FPGA ran the netlist evaluation at
> approximately 50MHz and the synthesis tools output indicated that this
> was the maximum this chip could do with this hardware description.
>
> If you just want a 6510 FPGA replacement: Forget about using the 6502
> net list and implement a high-level description of the 6502 plus the
> 6510 extras from scratch. It will be more compatible, easier to fix
> problems if any show up and require less power and a smaller FPGA.

For programming all you need is a usb/jtag programmer?

http://www.ebay.com/itm/Xilinx-Platform-USB-Download-Cable-J tag-Programmer-for-FPGA-CPLD-C-Mod-XC2C64A-/181100412793?pt= LH_DefaultDomain_0&hash=item2a2a6cff79

and using this module:

http://www.mirifica.it/store/lang-en/66-oho-elektronik-godil 40xc3s250e.html

Using jtag, is it possible to send information into the processor
while it's running? If I wanted to load a program into C64 memory
through the jtag, is this possible? Is it possible to record across
the jtag while the fpga is running - like all memory read addresses?

Thanks
Re: fpga 6502 [message #209847 is a reply to message #209846] Fri, 10 May 2013 05:57 Go to previous messageGo to next message
Ingo Korb is currently offline  Ingo Korb
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s1 <christianlott1@yahoo.com> writes:

> For programming all you need is a usb/jtag programmer?
>
> http://www.ebay.com/itm/Xilinx-Platform-USB-Download-Cable-J tag-Programmer-for-FPGA-CPLD-C-Mod-XC2C64A-/181100412793?pt= LH_DefaultDomain_0&hash=item2a2a6cff79

I'm not familiar with this particular one, but if it claims to support
Spartan 3E FPGAs it should work.

> and using this module:
>
> http://www.mirifica.it/store/lang-en/66-oho-elektronik-godil 40xc3s250e.html

That's the small one - if you really want to use the netlist simulation
you'll need the large one (GODIL40_XC3S500E) because the compiled
netlist occupies about 66% of the S500E. I have no idea how large a
proper implementation of a 6502 would be, but I suspect the small one
would suffice for that.

> Using jtag, is it possible to send information into the processor
> while it's running?

The Spartan 3E FPGA supports two user JTAG registers which should be
sufficient to implement such an interface. Of course you'd have to
implement both the processor side of the interface as well as the
software that talks to it.

If you want to manipulate the current CPU state (e.g. change register
values) you'll be better off by not using the netlist: In that form the
CPU offers basically the same access that you'd get from a real 6502
plus a set of read-only microprobing needles on the die to read values
from arbitrary locations. Adding a way to change the X register for
example would require analysis of the netlist to figure out the circuit
that implements it, modification of that circuit to add an external
"override" input and encoding that manipulation back in the netlist
format so the netlist-to-FPGA tool can optimize and recode the netlist
to Verilog.

> If I wanted to load a program into C64 memory
> through the jtag, is this possible?

If you implement it...

> Is it possible to record across
> the jtag while the fpga is running - like all memory read addresses?

That would require a bandwidth of approximately 2 MBytes/s just for the
addresses, i.e. a JTAG clock rate of 16MHz. The Spartan 3E supports a
maximum JTAG clock of 30MHz, so it might work. A dedicated interface or
an internal trace buffer that is later read at slower speed sounds like
a better idea though.

-ik
Re: fpga 6502 [message #209849 is a reply to message #209847] Fri, 10 May 2013 23:34 Go to previous messageGo to next message
christianlott1 is currently offline  christianlott1
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On May 10, 4:57 am, Ingo Korb <use...@mail.snowcat.de> wrote:
> s1 <christianlo...@yahoo.com> writes:
>> For programming all you need is a usb/jtag programmer?
>
>> http://www.ebay.com/itm/Xilinx-Platform-USB-Download-Cable-J tag-Progr...
>
> I'm not familiar with this particular one, but if it claims to support
> Spartan 3E FPGAs it should work.
>
>> and using this module:
>
>> http://www.mirifica.it/store/lang-en/66-oho-elektronik-godil 40xc3s250...
>
> That's the small one - if you really want to use the netlist simulation
> you'll need the large one (GODIL40_XC3S500E) because the compiled
> netlist occupies about 66% of the S500E. I have no idea how large a
> proper implementation of a 6502 would be, but I suspect the small one
> would suffice for that.
>
>> Using jtag, is it possible to send information into the processor
>> while it's running?
>
> The Spartan 3E FPGA supports two user JTAG registers which should be
> sufficient to implement such an interface. Of course you'd have to
> implement both the processor side of the interface as well as the
> software that talks to it.
>
> If you want to manipulate the current CPU state (e.g. change register
> values) you'll be better off by not using the netlist: In that form the
> CPU offers basically the same access that you'd get from a real 6502
> plus a set of read-only microprobing needles on the die to read values
> from arbitrary locations. Adding a way to change the X register for
> example would require analysis of the netlist to figure out the circuit
> that implements it, modification of that circuit to add an external
> "override" input and encoding that manipulation back in the netlist
> format so the netlist-to-FPGA tool can optimize and recode the netlist
> to Verilog.
>
>> If I wanted to load a program into C64 memory
>> through the jtag, is this possible?
>
> If you implement it...
>
>> Is it possible to record across
>> the jtag while the fpga is running - like all memory read addresses?
>
> That would require a bandwidth of approximately 2 MBytes/s just for the
> addresses, i.e. a JTAG clock rate of 16MHz. The Spartan 3E supports a
> maximum JTAG clock of 30MHz, so it might work. A dedicated interface or
> an internal trace buffer that is later read at slower speed sounds like
> a better idea though.
>
> -ik

Thank you for this information.

Last question - can this be used to emulate the VIC-II chip?

Thanks
Re: fpga 6502 [message #209850 is a reply to message #209849] Sat, 11 May 2013 06:27 Go to previous messageGo to next message
Ingo Korb is currently offline  Ingo Korb
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s1 <christianlott1@yahoo.com> writes:

> Last question - can this be used to emulate the VIC-II chip?

You'd have to add some circuits to generate an analog output signal from
the digital I/Os of the FPGA and for boards using the older 65xx VIC
also an adapter so the 12V on the VIC socket are not fed to the FPGA.

Oh, and obviously you'll have to implement a VIC-II from scratch in
Verilog or VHDL.

-ik
Re: fpga 6502 [message #209851 is a reply to message #209850] Sat, 11 May 2013 16:07 Go to previous messageGo to next message
christianlott1 is currently offline  christianlott1
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On May 11, 5:27 am, Ingo Korb <use...@mail.snowcat.de> wrote:
> s1 <christianlo...@yahoo.com> writes:
>> Last question - can this be used to emulate the VIC-II chip?
>
> You'd have to add some circuits to generate an analog output signal from
> the digital I/Os of the FPGA and for boards using the older 65xx VIC
> also an adapter so the 12V on the VIC socket are not fed to the FPGA.
>
> Oh, and obviously you'll have to implement a VIC-II from scratch in
> Verilog or VHDL.
>
> -ik

Now at least I know what and why (not). Thanks.
Re: fpga 6502 [message #209857 is a reply to message #209845] Mon, 13 May 2013 12:02 Go to previous message
Groepaz is currently offline  Groepaz
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s1 wrote:

> On May 9, 8:29 am, Groepaz <groe...@gmx.net> wrote:
>
>> emulating the 6502/10 is not the problem - its the other features you
>> want. eg it is not possible to "pause" the c64 by halting the cpu, the
>> vic will always continue running and doing its thing, and so will the
>> cias - so its not really a useful debug setup at all. (an emulator, such
>> as vice, can do this perfectly on the other hand)
>
> I see what you are saying. In this case, pausing the processor, you
> would need to pause cia registers before you paused the processor with
> a few sta $DDxx $DCxx to the timers beforehand.

and then you have the problem every classic freezer on c64 has - since you
can not read the timer compare value, you must do some stunts to try to
determine it anyway. and then when you want to restart, you'll again have to
do more stunts to restart the timers properly (which never works 100% in
practise). again, an emulator can do this a lot better.

> I don't see how the
> vic would be hurt by the processors absence from the bus.

the problem is that the vic will continue drawing and fetching data. when
you resume, it will not resume where you stopped but at an arbitrary
position. similar problem as with the cias, and again emulator can do it
perfectly :)

> You are probably right in the end, I just don't understand the reasons
> yet.

imagine single stepping through a complex program that uses timer- and vic
interrupts. stopping the cpu will not prevent either chip to fire
interrupts. so to prevent things from crashing when you restart, you must
disable all interrupts while the cpu is haltet. that however means that you
must restore them when resuming - in a cycle exact way so that the program
you are debugging doesnt note the difference. that is simply not possible to
do 100% on real hardware (but almost trivial in an emulator).

> And since this chip already exists I guess that other stuff I
> mentioned (wireless, piggy backed original) isn't necessary. The
> effort wouldn't fit the demand/desire.
>
> Thanks for responding.

--

http://www.hitmen-console.org http://magicdisk.untergrund.net
http://www.pokefinder.org http://ftp.pokefinder.org

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