Message-ID: <399@intelca.UUCP>
Date: Mon, 10-Sep-84 17:56:45 EDT
Article-I.D.: intelca.399
Posted: Mon Sep 10 17:56:45 1984
Date-Received: Sun, 16-Sep-84 10:32:23 EDT
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 21

(does net.digital exist?  we don't have it locally...)

Anyway, does anyone know if tri-state outputs on PALs are guaranteed
not to glitch entering/leaving tri-state?  Here is what I need: the
function is driven high, then tri-stated.  All during the time it
is tri-stated, the function remains high.  It then goes out of tri-state
before the function is driven low.  Finally, after it is out of
tri-state the function is driven low.  At each of the transitions
into and out of tri-state, it is very important that the output not
glitch low!  Of course, the output will be provided with some kind
of tie-up resistor.  What I need is some kind of confirmation that
PAL outputs (or any tri-state gate outputs, for that matter) don't
do funny things going into and out of tri-state.
-- 
I've got one, two, three, four, five senses working overtime, 
	trying to take this all in!

Ken Shoemaker, Intel, Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!kds
	
---the above views are personal.  They may not represent those of Intel.

Message-ID: <3659@decwrl.UUCP>
Date: Mon, 17-Sep-84 13:49:36 EDT
Article-I.D.: decwrl.3659
Posted: Mon Sep 17 13:49:36 1984
Date-Received: Tue, 25-Sep-84 05:57:23 EDT
Sender: daemon@decwrl.UUCP
Organization: DEC Engineering Network
Lines: 22

> Anyway, does anyone know if tri-state outputs on PALs are guaranteed
> not to glitch entering/leaving tri-state? 

> Ken Shoemaker, Intel, Santa Clara, Ca.

I asked Bill Collins of National Semi to investigate the question of 
glitches on PLA outputs during enable transitions, and I have Bill's
permission to quote his answer, which was given after he spent some time
both looking at the circuitry and at the bench.  National's PALs do NOT
glitch when the tri-state enable is changed, either to ENable or to
DISable.  They simply change from the high impedance state to the
asserted logic state when enabled, or from assertion to high impedance
when disabled.  This statement is not guaranteed to be true for MMI or
AMD or anyone else's PALs... 

Cheers,
Dick Binder   (The Stainless Steel Rat)

UUCP:  { decvax, allegra, ucbvax... }!decwrl!dec-rhea!dec-dosadi!binder
ARPA:  binder%dosadi.DEC@decwrl.ARPA

Posted Monday 17th September 1984, 13:53 EDT by DOSADI::BINDER