Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!udel!burdvax!barry From: barry@PRC.Unisys.COM (Barry Traylor) Newsgroups: comp.arch Subject: Re: Bandwidth Wasters Hall of Fame for comp.arch Summary: Stack machines are not dead! Keywords: Stack, mutlitasking, registers, etc., etc. Message-ID: <11539@burdvax.PRC.Unisys.COM> Date: 24 Sep 89 07:00:13 GMT References: <13744@well.UUCP> <4186@bd.sei.cmu.edu> <10732@eerie.acsu.Buffalo.EDU> <125156@sun.Eng.Sun.COM> Followup-To: comp.arch Distribution: na Organization: Unisys Corporation, Paoli Research Center; Paoli, PA Lines: 35 In article <125156@sun.Eng.Sun.COM> khb@sun.UUCP (chiba) writes: > >When the world was young(er) :> , stack machines, register machines, >and direct memory machines (e.g. TI) battled for domination. Before >reasonable register allocation algorithms were discovered stack >machines were nifty ... but now having a lot (use your own figure of >merit :>) of registers and good allocation is generally >conceeded to be the short path to good performance. >... >Bottom line: A stack machine derives less benefit from locality of > data reference. Stack machines OPTIMIZE locality of reference. By doing such, a processor does not need to have massive quantities of registers available. On a context switch, or better yet, a process switch (which on most machines involves 2 context switches), how long does it take to store and restore all of those registers? I remember reading in this forum that on a 40Mhz SPARC machine, it took about 70microseconds to do a context switch. It takes much less than that on a 16MHz A17. At the worst, a process switch costs 20microseconds. A context switch into the operating system costs less than 5 microseconds. A large part of the savings comes from the ability of the PROCESSOR to schedule internal registers and make sure that ONLY those that are needed immediately are valid. Top of stack is then chained through operators with a different top of stack register set for each pipelined operation. If an interrupt occurs, only those registers representing the current top of stack for the interrupted operator need to be pushed, not the entire register set. The registers allocated for operations subsequent to the interrupt are merely returned to the available pool. Options are my own. Measurements are approximate, but not far off. Barry Traylor Unisys A Series Engineering barry@prc.unisys.com