Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!um-math!sharkey!cfctech!teemc!hpftc!zardoz!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!usc!ginosko!gem.mps.ohio-state.edu!csd4.csd.uwm.edu!bbn!bbn.com!dswartz From: dswartz@bbn.com (Dan Swartzendruber) Newsgroups: comp.arch Subject: Re: Instruction (dis)continuation Message-ID: <44908@bbn.COM> Date: 28 Aug 89 21:55:08 GMT References:<1989Aug24.215104.156@mentor.com> <231@ssp1.idca.tds.philips.nl> <2345@oakhill.UUCP> <204@bbxeng.UUCP> <5990@pt.cs.cmu.edu> <205@bbxeng.UUCP> Sender: news@bbn.COM Reply-To: dswartz@BBN.COM (Dan Swartzendruber) Organization: Bolt Beranek and Newman Inc., Cambridge MA Lines: 12 Clearly it has to make some difference, given that the 680x0 processors support auto-increment/decrement of address registers! The PDP-11 had the same problem. I seem to recall they solved it by having a diagnostic register in which the CPU wrote which registers had been incremented or decremented and by how much. That wasn't as bad as it might first seem. There are only two registers which can change as a result of any given instruction and they could only change by 1, 2 or 4. It's been a while since I hacked on a PDP-11, so I might be off a little here, but that was the basic gist.... Maybe the 68040 does something similar? It certainly can't be any uglier than the sh*t the current processors have with eight gazillion different types of fault frames which can change incompatibly as the microcode is updated....