Xref: utzoo comp.arch:11594 comp.sys.ibm.pc.rt:1006 Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!agate!bionet!ames!amdcad!cayman!tim From: tim@cayman.amd.com (Tim Olson) Newsgroups: comp.arch,comp.sys.ibm.pc.rt Subject: Re: integer alignment problems on RT Message-ID: <27598@amdcad.AMD.COM> Date: 2 Oct 89 13:57:42 GMT References: <162@eliza.edvvie.at> Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Austin, TX Lines: 24 Summary: Expires: Sender: Followup-To: In article <162@eliza.edvvie.at> johnny@edvvie.at (Johann Schweigl) writes: | This leads me to the final questions: | - is it acceptable that the CPU changes the adress you delivered without any | warning and does something you wouldn't expect I don't think it is acceptable if there is no other option. However, this behaviour is potentially useful (the lower address bits may be used as tags for dynamic data-typing systems). | - how do other CPU's behave (eg. 88000, 68000, SPARC, MIPS) | - would you prefer getting an 'alignment violation trap' or something like this | - does any CPU implement such a trap The Am29000 implements an Unaligned Access Trap enable bit (TU) in the protected Current Processor Status Register which enables this trap on a process-by-process basis. If enabled, unaligned word and half-word accesses cause an Unaligned Access trap, placing the offending accesses' virtual address, data, and control information in special registers for use in the trap handler. The handler can be written to either abort the process (SIGSEGV) or emulate the transfer and return. -- Tim Olson Advanced Micro Devices (tim@amd.com)