Path: utzoo!attcan!uunet!ginosko!uakari.primate.wisc.edu!ames!pacbell!indetech!fiver!palowoda
From: palowoda@fiver.UUCP (Bob Palowoda)
Newsgroups: comp.unix.i386
Subject: Re: Mylex SCSI Controller
Message-ID: <831@fiver.UUCP>
Date: 30 Sep 89 10:12:54 GMT
References: <372@csense.UUCP>
Organization: Fiver Communications  Fremont, Ca
Lines: 54

From article <372@csense.UUCP>, by bote@csense.UUCP (John Boteler):
> From article <19245@gatech.edu>, by ken@gatech.edu (Ken Seefried III):
>> In article <369@csense.UUCP> bote@csense.UUCP (John Boteler) writes:
>>>Curious as to how a SCSI host controller can easily perform 
>>>cache operations?
>> the DPT controller for some excellent commentary, pro and con, on
>> the issues involved in caching disk controllers...
> 
> I don't need to.
> 
> I talked to one of the engineers from DPT at Comdex. He explained
> to me the difficulty of caching a SCSI host controller: since
> the controller handles up to seven devices on the SCSI bus,
> putting the cache system on the controller makes for little
> improvement, if any.

 Did DPT do a display a real comparison of throughput at Comdex?
 Does DPT manufacture a SCSI cacheing controller?

 The only reason I mention this is if I where at Comdex showing 
 off my ESDI controller. I surely would build your confidence 
 in the product. But I don't think it a fare comparison between
 these two types of controllers.

 A better comparison of the DPT would be to that of Adaptec's
 new ESDI cacheing controller.

> The best solution, and one which has
> been implemented by at least one drive manufacturer, is to
> put the caching components on the SCSI drive. 

  I thought SCSI drives have buffers?

> 
> When a SCSI request is sent to the drive by the controller, the
> controller is free to service one of the other six devices on
> the bus and the drive can check its own cache for the presence
> of the data requested and respond accordingly.

  Won't the Mylex controller service the request from the cache?

  Another thing about the Mylex controller, it is 32 bit. 
  DPT is 16 bit I believe. 

  Something else I don't quite understand is how they sync it with
  the cpu cycle.  

---Bob

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