Path: utzoo!attcan!uunet!wuarchive!mailrus!bcm!shell!storkel
From: storkel@limpet.shell.com (S. Storkel)
Newsgroups: comp.arch
Subject: Need info on SPARC & MIPS
Message-ID: 
Date: 27 Sep 89 20:55:36 GMT
Sender: usenet@shell.com
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Organization: Shell Development Company, Bellaire Research Center, Houston, TX
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I need some pointers to information on the SPARC and MIPS reduced
instruction set processors. I am mainly interested in the architecture
of these chips. Things like pipelines, instruction formats,
instruction types, exceptions, interrupt handling, data
representation, etc. I have access to Sun's SPARC Architecture Manual
and RISC Tutorial, but I'm looking for more detailed information on
the actual implementation.

If anybody could help me out here, I really appreciate it. Please
reply to:

		storkel@rice.edu	...!{uunet, sun}!rice!storkel

if possible. Thanks for the help.



						-- Scott Storkel



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