Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!phri!roy
From: roy@phri.UUCP (Roy Smith)
Newsgroups: comp.sys.mac
Subject: Re: Nix on mixing memory speeds?
Message-ID: <4007@phri.UUCP>
Date: 23 Sep 89 16:48:37 GMT
References: <11979@cit-vax.Caltech.Edu> <4002@phri.UUCP> <2040@leah.Albany.Edu> <1989Sep23.010904.7650@NCoast.ORG>
Reply-To: roy@phri.UUCP (Roy Smith)
Distribution: usa
Organization: Public Health Research Inst. (NY, NY)
Lines: 59

In <1989Sep23.010904.7650@NCoast.ORG> allbery@ncoast.ORG (Brandon S. Allbery):
> He [i.e. me] was insulting only to the person who claimed to the original
> poster that the memory speeds *had* to match. [...] There is, by and large,
> only *one* case where the memory speeds would have to match: if the memory
> storage system accesses more than one memory chip at the same time, all of
> those chips must be the same speed or the memory access hardware will get a
> severe case of heartburn.

	Again, bullshit.  OK folks, let's go over this slowly.  When a RAM
chip is is given a speed rating, what that means is the *minimum* amount of
time it takes for the chip to make sure that the data being presented on its
output data pin(s) is stable and valid.  It holds it there for as long as the
address and stobe signals stay constant.

	Follow this example.  You're a memory controller, I'm a ram chip.
You are designed to operate with 120ns chips.  I claim to be such a 120ns
chip.  You give me an address and tell me that you want to access that
address for reading.  Then you say "OK, start NOW!"  I putter around inside,
pull out the data, and put it on my output pin.  Since I promise 120ns access
time, sometime within 120ns after you said "NOW", I've got that data ready
for you, and I'll hold it there waiting for you until you tell me I can let
go.  Since you're designed for 120ns chips, you probably wait about 125ns,
read the data I've presented, and tell me you've got it.

	Now, imagine I'm a 100ns (or 80ns, or whatever, as long as it's less
than 120ns) chip.  You tell me what you want and say "START NOW".  Since I'm
promising 100ns read times, I make sure I get that data to you in 100ns.
Since you're a 120ns controller (with the same built-in 5ns timing error
margin), you grab the data 125ns after you said "NOW".  I had it ready at
100ns, but no problem, I'm perfectly willing to sit and twiddle my thumbs for
25ns until you get your act together, read the data pin, and tell me you've
got it.  In fact, you don't even *know* I'm a 100ns chip.  All you know is
that you demand I be ready in 120ns or less, and couldn't care (and wouldn't
notice) if that means 119.5ns or 65ns.  Just don't let it be 121ns or we
might be in trouble (actually, since you're willing to allow an extra 5ns
slop, I'll probably get away with 121ns, but not 126ns).

	OK, now imagine you're doing 32-bit wide transfers.  Me and my three
brothers are all lined up side by side (in this case, one "brother" is
actually 8 chips on a SIMM, but the same argument could hold for chips within
a SIMM).  I'm a 120ns SIMM, two of my brothers are 100ns SIMMs, and the other
brother is a 80ns SIMM.  You give us all the address information and say
"NOW".  sometime before 80ns is up, the guy on the end has his data ready and
starts twiddling his thumbs.  Sometime in the next 20ns, the two guys in the
middle get their act together and go into thumb-twiddling mode.  Eventually,
sometime before 120ns has elapsed from when you said "NOW", I'm ready.  At
125ns, just like always, you grab the data we've got ready waiting for you.
You don't know if that data has been read for 5ns or 45ns (in fact, some of
it has been ready for the former, some for the latter, and some inbetween).
Once you've got it, you tell us all your're done with us, and we go do
whatever it is dram chips do when they are not being accessed (dribbling
little bits of charge on the floor, I guess).  No mess, no fuss, no memory
heartburn.  You may have wasted some money on chips that were faster than you
needed (or could use), but you won't have any memory problems.
-- 
Roy Smith, Public Health Research Institute
455 First Avenue, New York, NY 10016
{att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu
"The connector is the network"