Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!sun-barr!cs.utexas.edu!uunet!pilchuck!amc-gw!thebes!mtk!marmar From: marmar@mtk.UUCP (Mark Martino) Newsgroups: comp.lang.forth Subject: Cost of Forth Chips Summary: Simpler should be cheaper Message-ID: <893@mtk.UUCP> Date: 15 Aug 89 17:29:19 GMT Reply-To: marmar@mtk.UUCP (Mark Martino) Distribution: usa Organization: Mannesmann Tally, Kent, WA 98032 Lines: 25 I was reading an article by Brian Case in the August issue of "Microprocessor Report". He brought up two issues that bugged me a little. I was wondering what the rest of you think about his ideas. After a fairly even-handed comparison of Forth chips versus RISC chips (with a slight bias towards non-Forth languages), he asserts that using a Forth based system will end up being about as expensive as a RISC based system. I found it hard to disagree with him, even though I would like to use Forth and Forth chips. This reminded me of a question for which I still do not have an answer. Why are the RTX2000 and the SC32 more expensive than RISC chips? Despite the economies of large volume production, I thought that implementing Forth in silicon would be relatively cheap since it takes comparatively fewer gates than previous architectures. I realize everyone likes to make up their R & D costs, but both of these chips had a lot of their design work done before their current developers implemented them. The second issue has to do with the near future of Forth chips. In the last few paragraphs Brian concludes that in order to operate at clock rates greater than the current 10-12 MHZ, Forth chips will have to fall back to using pipelining as do RISC chips. He then says that Forth chips will look very much like RISC chips anyway. Will this really be necessary? Has anyone else seen this article? What do you think about his arguements?