Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!ucbvax!amdcad!cayman!tim From: tim@cayman.amd.com (Tim Olson) Newsgroups: comp.lang.forth Subject: Re: Cost of Forth Chips Message-ID: <26801@amdcad.AMD.COM> Date: 16 Aug 89 18:35:03 GMT References: <893@mtk.UUCP> <17173@ut-emx.UUCP> Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Distribution: usa Organization: Advanced Micro Devices, Austin, TX Lines: 21 Summary: Expires: Sender: Followup-To: In article <17173@ut-emx.UUCP> olorin@walt.cc.utexas.edu (Dave Weinstein) writes: | In article <893@mtk.UUCP> marmar@mtk.UUCP (Mark Martino) writes: | >[...] Brian concludes that in order to operate at clock rates greater | >than the current 10-12 MHZ, Forth chips will have to fall back to using | >pipelining as do RISC chips. | | NO!!! Bearing in mind that the designed use for most of these Forth | chips is in Realtime applications, adding pipelines is one of the worst | things you can do! Realtime applications need to be predictable (i.e. take | the same number of cycles to do the same thing each time), and throwing in | pipelines destroys that predictability (you get greater *overall* throughput | but actual mileage may vary). I don't believe Harris will do this (they have | been touting the predictability of the RTX family throughout their literature. This is not true. Pipelining per se does not affect determinism. Things like caches and interlocks on parallel functional units *can* affect it. -- Tim Olson Advanced Micro Devices (tim@amd.com)