Path: utzoo!utgpu!watmath!att!dptg!rutgers!cs.utexas.edu!csd4.milw.wisc.edu!lll-winken!xanth!nic.MR.NET!ns!logajan From: logajan@ns.network.com (John Logajan) Newsgroups: comp.sys.atari.st Subject: Re: 1Mbit DRAM Decoupling Message-ID: <1541@ns.network.com> Date: 9 Aug 89 07:00:08 GMT References: <3958@shlump.nac.dec.com> Sender: logajan@ns.network.com (John Logajan) Organization: Network Systems Corp. Mpls MN Lines: 24 In article <3958@shlump.nac.dec.com>, landry@enginr.dec.com writes: > cap value(uf) total voltage drop (mv) > > 0.068 130 > 0.1 115 > 0.22 95 > 0.33 85 > 0.47 80 Consider that the threshold voltages for TTL levels are 0.8 and 2.4, and closer to the rails for cmos -- then the difference between 0.115 and 0.085 (.03 volts) doesn't seem so bad. I agree that the noise margins are better for .33, but are they better enough? As an aside, one our technology guys was telling me that bypass caps of any size or type are virtually useless for eliminating the noise components above about 300mhz. Fortunately most logic is more prone to lower frequency (lower than 300mhz!) glitches than to higher frequency glitches -- after all, if it could respond that fast, people would use it in their Cray's instead of their ST's. -- - John M. Logajan @ Network Systems; 7600 Boone Ave; Brooklyn Park, MN 55428 - - logajan@ns.network.com / ...rutgers!umn-cs!ns!logajan / john@logajan.mn.org -