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From: olorin@walt.cc.utexas.edu (Dave Weinstein)
Newsgroups: comp.lang.forth
Subject: Re: Cost of Forth Chips
Message-ID: <17225@ut-emx.UUCP>
Date: 17 Aug 89 13:36:00 GMT
References: <893@mtk.UUCP> <17173@ut-emx.UUCP> <26801@amdcad.AMD.COM>
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Reply-To: olorin@walt.cc.utexas.edu (Dave Weinstein)
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In article <26801@amdcad.AMD.COM> tim@amd.com (Tim Olson) writes:
>In article <17173@ut-emx.UUCP> olorin@walt.cc.utexas.edu (Dave Weinstein) writes:
		[Pipelines --> Non-deterministic processor]

>This is not true.  Pipelining per se does not affect determinism. 
>Things like caches and interlocks on parallel functional units *can*
>affect it.

Right. (Sigh). I was assuming things not in the question (i.e. the instruction
cache along with the pipeline). Now the question is, how useful are pipelines
*without* cacheing and interlocks?

--Dave



--
Dave Weinstein			olorin@walt.cc.utexas.edu
(512) 339-4407 Home        	GEnie: DHWEINSTEIN
My employers never agree with me anyway.