Path: utzoo!utgpu!watmath!att!tut.cis.ohio-state.edu!brutus.cs.uiuc.edu!flute.cs.uiuc.edu!grunwald From: grunwald@flute.cs.uiuc.edu (Dirk Grunwald) Newsgroups: comp.arch Subject: Cycle Counter Message-ID:Date: 9 Aug 89 21:29:48 GMT Sender: news@brutus.cs.uiuc.edu Reply-To: grunwald@flute.cs.uiuc.edu Distribution: comp Organization: University of Illinois, Urbana-Champaign Lines: 27 Hi, Another ``how much does this cost'' question. When doing performance monitoring, benchmarking or profiling, you want a high-resolution timer. Some systems have microsecond timers, and those are considered pretty snazzy; I know I was overjoyed when I found one on the Encore. Normal machines, e.g., a Sun, have about 5 millisecond resolution. That's pathetic. How much would it cost to add an additional register that would be incremented each cycle? It doesn't need to flow through the ALU, it would be doing a single count-up. One could conjecture using a mode-flag to say ``yeah, count using this register'' -- if you didn't want to use the counter, you'd have one extra register to play with. I know something like this exists on the Cray X-MP; do other machines have cycle counters as well? Using a register has some advantages; it's a normal part of the processor state, reducing save/restore cost. Also, processes can have a virtual cycle counter, reflecting the cycle counter for that process alone. Being able to set it would mean that you might not care if it was only 32bits, since you set it to 0 to time routines. With a 20 nanosecond clock, it would only be good for 86 seconds, but that might be enough.