Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!cica!gatech!amdcad!cayman!tim From: tim@cayman.amd.com (Tim Olson) Newsgroups: comp.lang.forth Subject: Re: Cost of Forth Chips Message-ID: <26831@amdcad.AMD.COM> Date: 18 Aug 89 18:08:58 GMT References: <893@mtk.UUCP> <21351@cup.portal.com> <5882@pt.cs.cmu.edu> <26815@amdcad.AMD.COM> <5902@pt.cs.cmu.edu> Reply-To: tim@amd.com (Tim Olson) Distribution: usa Organization: Advanced Micro Devices, Austin, TX Lines: 20 Summary: Expires: Sender: Followup-To: In article <5902@pt.cs.cmu.edu> koopman@a.gp.cs.cmu.edu (Philip Koopman) writes: | Now, if a few microseconds for an interrupt latency is OK, then | pipelining works fine. But, if you want faster interrupt response, | you have a problem. The RTX 2000 takes 4 clock cycles (400 ns) between the | time an interrupt is asserted on a pin until it is actually executing | the first interrupt service instruction. The Am29000, a pipelined RISC processor, takes 7 cycles worst case from assertion of an interrupt pin to the first instruction of the interrupt handler entering the execute stage (using single-cycle external memory). At 40ns/cycle this is 280ns. Best case (hit in Branch Target Cache, array of interrupt handlers) can be as small as 3 cycles. This illustrates how pipelining can help -- the cycle time can be lowered enough that the resultant processor can be faster even if more cycles are required for exceptional conditions. -- Tim Olson Advanced Micro Devices (tim@amd.com)