Path: utzoo!utgpu!watmath!att!ucbvax!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!jk3k+
From: jk3k+@andrew.cmu.edu (Joe Keane)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <0YrsEMy00V4GQ=CJZw@andrew.cmu.edu>
Date: 9 Aug 89 01:08:40 GMT
References: <828@eutrc3.urc.tue.nl>,
	<26667@amdcad.AMD.COM>
Organization: Mathematics, Carnegie Mellon, Pittsburgh, PA
Lines: 15
In-Reply-To: <26667@amdcad.AMD.COM>

In article <26667@amdcad.AMD.COM> tim@cayman.amd.com (Tim Olson) writes:
>I know of no processors that have delayed branches and restrictions on
>delay instruction types.

The IBM RT manual says (rather verbosely IMHO):

Certain instructions are not allowed to be the subject of a branch with execute
instruction.  Since the branch with execute instructions change the normal
sequential execution of instructions, the subject instructions cannot be an
instruction that also changes the instruction sequencing; otherwise the
processor may be put in an unpredictable state.  Thus, all branches, jumps,
traps, Load Program Status, Supervisor Call, and Wait instructions cannot be
subject instructions.  The system processor provides hardware that detects
these illegal instructions and causes a program check interrupt if any of these
instructions occur as the subject of a branch with execute instruction.