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From: rtrauben@cortex.Sun.COM (Richard Trauben)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <120947@sun.Eng.Sun.COM>
Date: 11 Aug 89 15:02:31 GMT
References: <828@eutrc3.urc.tue.nl> <26667@amdcad.AMD.COM> <26676@amdcad.AMD.COM> <8266@hoptoad.uucp>
Reply-To: rtrauben@sun.UUCP (Richard Trauben)
Organization: Sun Microsystems, Mountain View
Lines: 44

In article <8266@hoptoad.uucp> gnu@hoptoad.uucp (John Gilmore) writes:
>tim@cayman.amd.com (Tim Olson) wrote:
>> Does anyone else know of other processors with such restrictions?
>I'm surprised that nobody mentioned the SPARC. 
Tim was informed off-line.

> SPARC has restrictions on which types of branches can sit in the delay 
> slot of which other types. I think in the first draft of the architecture 
> I was the one who noticed that the intended "return from interrupt" 
> sequence was one of the invalid ones!  

	The first draft of the architecture spec predates me. However, 
	branch couples where a return from trap instruction resides in the
	delay slot is perfectly legal sparc code. The primary use of the
	branch couple is to restart faulted instructions that reside in 
	the delay slot. Thus the sequence:

		a1:	 JMPL t1 (t1= address of instruction to restart)
		a2:  RETT t2 (t2= address of successor to restarted instruction)
		.
		.
		t1:	 I1		 (restarted fault instruction with exception)
		.
		.
		t2:  I2 	 (successor PC to faulted instruction) 
		t2+: I2+	 (successor to successor)
		.
		.
	will be executed as a1, a2, t1, t2, t2+.

>There's a serious catch to it on the SPARC:  the second instruction
>cannot be a delayed control transfer [i.e. a branch with a delay
>slot].  If it is, what the CPU does is undefined!

	Your memory is in error. The SPARC architecture no such requirement.  
	Branch couples require the first branch to be unconditional. The second
	is unconstrained. If the first branch does not meet the above requirement
	the behavior is implementation dependent. Table 4-12 of page 47 in the 
	rev 50 SPARC architecture manual (August 8,1987) identifies the behavior
	for all types of branch couples.

- Richard Trauben
  Sun Microsystems
  Mt View, California