Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!ucbvax!hplabs!pyramid!epimass!jbuck
From: jbuck@epimass.EPI.COM (Joe Buck)
Newsgroups: comp.arch
Subject: Re: hardware complex arithmetic support
Keywords: FFT complex arithmetic
Message-ID: <3532@epimass.EPI.COM>
Date: 17 Aug 89 18:36:27 GMT
References:  <1672@crdgw1.crd.ge.com> <5858@pt.cs.cmu.edu> <121828@sun.Eng.Sun.COM>
Reply-To: jbuck@epimass.EPI.COM (Joe Buck)
Organization: Entropic Processing, Inc., Cupertino, CA
Lines: 16

In article <121828@sun.Eng.Sun.COM> rtrauben@sun.UUCP (Richard Trauben) writes:
>The "current/previous" generation of ATT and Texas Instruments digital 
>signal processor (DSP) chips provide complex floating point arithmetic
>primitives to speed up the inner-loop multiply/accumulate butterfly 
>operation of a fast fourier transform.

There is no support for complex arithmetic per se in the TI TMS320
family, and I don't believe there is any in the AT&T chips either.
What is supported is a magic "bit reversal addressing" mode, which
makes it easy to handle the shuffling operation required in an FFT.

It requires four multiplies, an addition, and a subtraction to do a
complex multiply; you can do this in four cycles on the TMS320C30 by
taking advantage of parallel multiplication and addition/subtraction.
-- 
-- Joe Buck	jbuck@epimass.epi.com, uunet!epimass.epi.com!jbuck