Path: utzoo!attcan!utgpu!watmath!iuvax!mailrus!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Vectorizing division in a do loop
Message-ID: <44483@bbn.COM>
Date: 18 Aug 89 14:19:45 GMT
References: <112400003@uxa.cso.uiuc.edu>
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 44

In article <112400003@uxa.cso.uiuc.edu> gsg0384@uxa.cso.uiuc.edu writes:
>I've heard that vector machines are more expensive than multi-cpu parallel
>machines.  I've got two questions about vector machines.

It depends upon what you're comparing.  A Cray is more expensive than
a Sequent.  I know of vector machines that are cheaper than simple
single-processor scalar machines.  You statement may be a result of a
perception that "for a fixed MIPS, parallel processing is cheaper than
a single processor."  Which is a probably a valid statement, if your
application gets anywhere near linear speedup.

>1.  For compiler design, I think vector machine architecture is easier.
>    Is this true?

Today your statement is true.  The reason is that vector machines have
been around much much longer than parallel machines (in an industrial
sense) and there has been many more manyears of development put into
automatic vectorization.  Now that usable parallel machines (i.e,
shared global memory) exist, my guess is that compilation technology
for them will catch up to exploit the massive performance capacity.

>2. Our machine is Ardent Titan.  Each cpu has 64-register length vector
>   registers.  The problem is that this machine does not vectorize do loops
>   with division.  How much harder is to implement division than the other
>   three operations, + - x?  Is this a hardware limitation?

I am guessing, but it sounds like there is no vector divide instruction.
If their divider is a successive approximation type, especially if it
uses the multiplier, which is likely, it cannot be pipelined anyway.
BTW the Alliant has a standalone divider gate array.  Only one is used 
in scalar instructions.  But for vectors there are two of them, which
operate on alternate operand pairs.

>I'd rather have a vector machine than a multi-cpu parallel machine for 
>my application.  I just want more people in computer industries to pay
>more attention to vector machines.

For a vector machine you'll need to go to the minisupercomputer guys,
I'm afraid.  It looks like the suppliers of single-chip micros are not
to the point where they are (willing or able?) to include them.  Intel
has a first step with the dual instruction issue capability if the
i860, but they're not there yet; also their data cache is far too
small for it to be effective.
:-) Stan