Path: utzoo!attcan!uunet!cs.utexas.edu!usc!apple!bbn!oliveb!mipos3!smdvx1!hsit
From: hsit@smdvx1.intel.com (Hon P. Sit)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <691@mipos3.intel.com>
Date: 10 Aug 89 22:02:25 GMT
References: <828@eutrc3.urc.tue.nl> <26667@amdcad.AMD.COM> <2284@yogi.oakhill.UUCP>
Sender: news@mipos3.intel.com
Reply-To: hsit@smdvx1.UUCP (Hon P. Sit)
Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA
Lines: 13

In article <2284@yogi.oakhill.UUCP> cs.utexas.edu!oakhill!marvin (Marvin Denman) writes:
>
>The 88100 does have a separate adder for branches like most other chips with
>delayed branching, but the User's Manual explicitly states that for future
>compatibility the delay slot instruction cannot be a trap, jump, branch, or
>any other instruction that modifies the instruction pointer.  In other words
>this behavior, while it may be useful for at least one special case 
>application, is not guaranteed to work the same on all implementations of the
>architecture.  This allows the possibility of different pipelining schemes in
>the future without unduly tying the architect's hands.
>

The Intel i860 has the similar restrictions.