Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wasatch!cs.utexas.edu!uunet!virtech!dennis From: dennis@virtech.UUCP (Dennis P. Bednar) Newsgroups: comp.unix.i386 Subject: Re: Ethernet boards for ISC 386/ix Message-ID: <1024@virtech.UUCP> Date: 16 Aug 89 21:12:56 GMT References: <1423@hydra.gatech.EDU> <2642@dell.dell.com> Distribution: usa Organization: Virtual Technologies Inc Lines: 22 Summary: How about a figure of the daisy-chained PIC's? In article <2642@dell.dell.com>, james@raid.dell.com (James Van Artsdalen) writes: > > There are a number of reasons why IRQ 2 may not work. In particular, > some video cards (Video 7 16 bit comes to mind) drive IRQ 2 both active > *and* inactive. Also, on an AT compatible, the bus line labelled IRQ 2 > is actually connected to IRQ 9, since the real IRQ 2 is used to cascade > the second interrupt controller. > I'm still a little unclear on how the two PIC's (Programmable Interrupt Controller chips) are actually connected to the bus, to one another, and to the CPU. I have a vague idea that that there are 8 input IRQ lines per PIC, but that when you cascade two PIC's you don't get all 16 IRQ levels because of the daisy-chaining. I suppose there is only one INT_REQ (interrupt request) line that goes to the CPU, and depending on the IRQ pin and how the PIC's were daisy-chained you would get one one PIC responding with the interrupt vector number information. But I still can't picture how the bus is connected to the PIC's and to the CPU. Can someone draw a figure or elaborate in a little more detail please?