Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!amdahl!amdcad!cayman!tim From: tim@cayman.amd.com (Tim Olson) Newsgroups: comp.lang.forth Subject: Re: Cost of Forth Chips Message-ID: <26816@amdcad.AMD.COM> Date: 17 Aug 89 15:30:47 GMT References: <893@mtk.UUCP> <17173@ut-emx.UUCP> <26801@amdcad.AMD.COM> <17225@ut-emx.UUCP> Sender: news@amdcad.AMD.COM Reply-To: tim@amd.com (Tim Olson) Distribution: usa Organization: Advanced Micro Devices, Austin, TX Lines: 15 Summary: Expires: Sender: Followup-To: In article <17225@ut-emx.UUCP> olorin@walt.cc.utexas.edu (Dave Weinstein) writes: | Now the question is, how useful are pipelines | *without* cacheing and interlocks? Pipelining a processor is one way of helping to reduce the cycle time and increase performance. It does not require caches or other speedup techniques to be useful. One problem with pipelining is that conditional jumps tend to break the pipe, reducing the advantage of pipelining in programs that have many conditional non-sequential fetches. However, most of the non-sequential fetches in FORTH are unconditional (following the thread of control). -- Tim Olson Advanced Micro Devices (tim@amd.com)