Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!mit-eddie!uw-beaver!ubc-cs!alberta!calgary!enme3!deraadt
From: deraadt@enme3.ucalgary.ca (Theo Deraadt)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Denise/Paula/Agnus/Gary/Portia
Message-ID: <1702@cs-spool.calgary.UUCP>
Date: 12 Aug 89 09:51:05 GMT
References: <1388@bnr-fos.UUCP> <1671@cs-spool.calgary.UUCP> <12258@grebyn.com>
Sender: news@calgary.UUCP
Reply-To: deraadt@enme3.UUCP (Theo Deraadt)
Organization: U. of Calgary, Calgary, Alberta, Canada
Lines: 42

In article <12258@grebyn.com> ckp@grebyn.UUCP (Checkpoint Technologies) writes:
>In article I wrote...
>>I thought about what would be involved in using a TI 340x0 in an Amiga
>>system before. The format of the video memory leads me to say it's not
>>practical. The Amiga is bitplane oriented, as all the graphics.library
>>structures indicate, while the TI chipsets are pixelpacked.
>
>	Look at the way graphics memory for the Bridgecard is arranged.
>It's addressed in three different locations, and in each one, the same
>memory is organized differently. I can easily imagine that a simple
>system can be devised to make the same region of memory look both
>pixel-packed and bit plane'd. Then, both the graphics.library and the
>34020 would be happy.

No, there are still major problems. Ok, let's not talk 34020 yet, it's
not out yet. The methods used to communicate to the 34010 are pretty
bogus. You have a 16bit databus, and a little address bus. You have
access to a couple of registers inside the chip. One of the registers
is an address register. Another is a control register that specifies
whether the address is to remain the same, or increment each read/write
cycle. Another register is a data register, read/write a value to here,
and it gets interleaved with the 34010's memory accesses. The address
register also gets incremented if you set a control bit... Ok that's
probably not exactly it, but not far off,.. I don't have the book on
my shelf anymore.. Ok, so you can't use that port to talk to the memory.
It's not a high performance bus, to say the least.

Now you are talking about letting the Amiga dual port into the 34010's
video rams. That's bloody scary. A friend and I just dual ported a 68020
and an ACRTC in static rams. Video rams are sorta like DRAMS.. sorta..
Ugh. Scary.

What you are saying, is that if you have a bitmap in a program, and you
want to blit in it, you are going to use the 68000 to blit it into the
34010 memory. Of course! It does not have access to the memory where the
program has kept it's data. And transferring that little bitmap (wherever
in memory it is) into pixel packed format so the 34010 can blit it in is
not much better than letting the 68000 just blit it in itself. WHAT'S
the the 34010 for then? Sounds like a doomed project to me...