Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!ubc-cs!van-bc!
From: lphillips@lpami.wimsey.bc.ca (Larry Phillips)
Newsgroups: comp.sys.amiga
Subject: Re: A1000 Rejuvenator Project
Message-ID: <702@lpami.wimsey.bc.ca>
Date: 17 Aug 89 21:31:38 GMT
Lines: 28
Return-Path: 
To: van-bc!rnews

In <22000@louie.udel.EDU>, 451061%UOTTAWA.bitnet@ugw.utcs.utoronto.ca (Valentin Pepelea) writes:
>dougp@voodoo.ucsb.edu writes in message <2215@hub.UUCP>
>
>> Could the Rejuvenator have been designed to use dual ported ram to allow
>> both the 68000 and the custom chips simualtanious access to CHIP RAM?
>> Or is there something in the way the custom chips work that would
>> prevent this from working?
>
>Over here in Ottawa, we call dual ported ram, a block of memory which can
>be accessed both through 16-bit and 32-bit buses. What you are talking about
>is interleaved ram, so that you can access a small block of ram through one bus
>while accessing another block through another bus. A little like CHIP and FAST
>ram are.

Only 16 and 32 bit buses? Poor Ottawans, stuck with such limited dual ported
rams.  Last I looked, it didn't matter whether it was a 1 or 128 bit bus.  Dual
ported ram is dual ported ram, period.  Assumptions about what he is talking
about based upon limited definitions are amusing, but not particularly relevant.

-larry

--
"So what the hell are we going to do with a Sun?" - Darlene Phillips -
+-----------------------------------------------------------------------+ 
|   //   Larry Phillips                                                 |
| \X/    lphillips@lpami.wimsey.bc.ca -or- uunet!van-bc!lpami!lphillips |
|        COMPUSERVE: 76703,4322  -or-  76703.4322@compuserve.com        |
+-----------------------------------------------------------------------+