Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!cica!tut.cis.ohio-state.edu!pt.cs.cmu.edu!a.gp.cs.cmu.edu!koopman From: koopman@a.gp.cs.cmu.edu (Philip Koopman) Newsgroups: comp.lang.forth Subject: Re: Cost of Forth Chips Summary: Harris isn't going to pipeline... Message-ID: <5882@pt.cs.cmu.edu> Date: 17 Aug 89 13:07:37 GMT References: <893@mtk.UUCP> <21351@cup.portal.com> Distribution: usa Organization: Carnegie-Mellon University, CS/RI Lines: 50 I'm not going to bore everyone with a bunch of excerpts, but there has been a conversation about costs and design options for Forth chips that I would like to comment on. System costs for the high-end RISC processors are *much* more expensive than stack-based chips (e.g. about $2500 per chip set for an 88K last time I checked). Don't be fooled by systems that have a reasonable processor cost and then require MMUs before they will work at all. Forth processors can have smaller memories (and therefore system costs) because they introduce a much smaller run-time penalty for heavy subroutine reuse. On the RTX-32P, subroutine calls cost about 0.7 clocks, and subroutine returns about .2 clocks, on the average (if memory serves). Of course the SC32 is expensive now, because they don't have that big a market built up yet. The RTX 2000 can be discounted if you want to order a few thousand. That's the same as with all chips. Although the RTX 2000 has a small core, it also has two on-chip stacks and a hardware multiplier, which run up the die size a lot, and therefore the cost. > > I realize everyone likes to make up their > >R & D costs, but both of these chips had a lot of their design work done > >before their current developers implemented them. 1) Do you think the original designers gave away their work for free? 2) The Novix chip was broken in many respects, and a *lot* of redesign was done. On the topic of memory bandwidth, there is no inherent reason why stack machines should have a memory access problem. The RTX 2000 memory bandwidth bottleneck is a direct result of Chuck Moore's philosophy that fast memory was cheap (since he probably didn't need more than 8K words for any of his programs anyway). I have proved to myself that clock speeds and effective processing rate can be improved by a significant amount, even using the same fabrication process and perhaps even slower memory chips. It's all in how you look at the problem and approach the design. Pipelining does not affect the consistency of response in a real time program, but it does affect the interrupt response latency, since you have all that state to save when processing an interrupt. There is absolutely no requirement to pipeline stack processors in the RISC fashion in order to get significantly higher performance. Phil Koopman koopman@greyhound.ece.cmu.edu Arpanet 2525A Wexford Run Rd. Wexford, PA 15090 Senior Scientist at Harris Semiconductor. I don't speak for them, and they don't speak for me.