Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!cica!gatech!udel!mmdf From: 451061%UOTTAWA.bitnet@ugw.utcs.utoronto.ca (Valentin Pepelea) Newsgroups: comp.sys.amiga Subject: Re: A1000 Rejuvenator Project Message-ID: <22000@louie.udel.EDU> Date: 18 Aug 89 20:32:54 GMT Lines: 20 dougp@voodoo.ucsb.edu writes in message <2215@hub.UUCP> > Could the Rejuvenator have been designed to use dual ported ram to allow > both the 68000 and the custom chips simualtanious access to CHIP RAM? > Or is there something in the way the custom chips work that would > prevent this from working? Over here in Ottawa, we call dual ported ram, a block of memory which can be accessed both through 16-bit and 32-bit buses. What you are talking about is interleaved ram, so that you can access a small block of ram through one bus while accessing another block through another bus. A little like CHIP and FAST ram are. Valentin _________________________________________________________________________ The godess of democracy? "The Name: Valentin Pepelea tyrants may destroy a statue, Phonet: (613) 231-7476 but they cannot kill a god." Bitnet: 451061@Uottawa.bitnet Usenet: Use cunyvm.cuny.edu gate - Confucius Planet: 451061@acadvm1.UOttawa.CA