Path: utzoo!utgpu!watmath!att!dptg!ulysses!andante!alice!jmk
From: jmk@alice.UUCP (Jim McKie)
Newsgroups: comp.arch
Subject: Re: Cycle Counter
Message-ID: <9786@alice.UUCP>
Date: 17 Aug 89 04:12:47 GMT
Organization: AT&T Bell Laboratories, Murray Hill NJ
Lines: 28


The Crisp CPU has the following register:

	Timer
	The timer is a 28 bit internal register which can be incremented
	every cpu clock cycle or at the completion of every instruction.
	The timer can also, optionally, interrupt the cpu when the count
	overflows. When read, the least significant bit of the timer appears
	on bit 4 of the resultant data and the low-order four bits are
	always zero. The timer is both readable and writeable, and the 
	counting function is controlled by the low three bits, which are
	write only. These timer register bits are used to configure the
	timer:

	- bit 0. When clear, the timer counts cycles. When set, the timer
	  counts completed instructions (folded branches do not count).
	- bit 1. When clear, the timer is on all the time (with reference
	  to bit 0). When set, the timer only counts when the PSW indicates
	  User execution level.
	- bit 2. When set, the timer will generate a timeout exception, not
	  an interrupt, when it overflows (goes from 0 to non-zero). It has
	  precedence over all exceptions except zero divide. Interrupts
	  have precedence over time outs.

A similar register was added to the locally-developed 68020-based grey-scale
bitmap terminal and has been used as the basis for a debugger.

Jim McKie	research!jmk -or- jmk@research.att.com