Path: utzoo!utgpu!watmath!att!tut.cis.ohio-state.edu!cs.utexas.edu!usc!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!ucla-cs!oahu!marc
From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Re: Context-switch times
Message-ID: <26502@shemp.CS.UCLA.EDU>
Date: 17 Aug 89 16:28:13 GMT
References: <7408@microsoft.UUCP>
Sender: news@CS.UCLA.EDU
Reply-To: marc@cs.ucla.edu (Marc Tremblay)
Organization: UCLA Computer Science Department
Lines: 14

In article <7408@microsoft.UUCP> gideony@microsoft.UUCP (Gideon Yuvall) writes:
>What is a realistic context-switch penalty for the MIPS, SPARC,
>88K, i860 (...) RISC chips? 

Quoted from IEEE Micro, August 1989:
"A typical i860 CPU context switch, including the data cache flush,
takes approximately 65 microseconds."
For a 40MHz part, 65 microseconds represent 2600 cycles. 
This includes among other things, invalidating the instruction cache, 
saving the various on-chip registers, and saving dirty lines
of the data cache to main memory (for write-back policy).

					Marc Tremblay
					marc@CS.UCLA.EDU