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From: cik@l.cc.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: hardware complex arithmetic support
Message-ID: <1502@l.cc.purdue.edu>
Date: 16 Aug 89 12:38:41 GMT
References:  <1672@crdgw1.crd.ge.com>
Organization: Purdue University Statistics Department
Lines: 27

In article <1672@crdgw1.crd.ge.com>, davidsen@sungod.crd.ge.com (ody) writes:
> In article  jk3k+@andrew.cmu.edu (Joe Keane) writes:
> 
  | Are there any architectures that have hardware support for complex arithmetic?
  | For example, dividing two complex numbers (in rectangular form) takes 6
  | multiplications, 2 divisions, and 3 add/subtracts, if i count correctly.  With
  | appropriate functional units that can be hooked up in the right way, this could
  | be done in a couple of clock cycles.
> 
>   Actually I didn't write the pseudo-microcode, but I *think* the
> minimum time is the sum of mpy,div,add for the longest path. And none of
> those happen in a few cycles unless you pipeline.

With the maximum amount of parallelism, the multiplications can be done in
parallel, the adds in parallel, and the divides in parallel.  One could
even combine the multiplies and adds.  But that is it.

Hardware support for complex add would not be too difficult, nor complex
multiply.  It would be more expensive than hardware support for good
integer arithmetic, which is almost nonexistent now.

The fastest time for complex multiplication would be slightly worse than
double precision multiplication, but division would slow down as usual.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet, UUCP)