Path: utzoo!attcan!uunet!peregrine!ccicpg!cci632!rit!tropix!moscom!ur-valhalla!uhura.cc.rochester.edu!rochester!rutgers!apple!ames!haven!adm!smoke!gwyn From: gwyn@smoke.BRL.MIL (Doug Gwyn) Newsgroups: comp.unix.wizards Subject: Re: Information on SPARC assembly (atomic Test and Set) Message-ID: <10419@smoke.BRL.MIL> Date: 22 Jul 89 02:02:04 GMT References: <350@osc.COM> <577@lakart.UUCP> Reply-To: gwyn@brl.arpa (Doug Gwyn) Organization: Ballistic Research Lab (BRL), APG, MD. Lines: 12 In article <577@lakart.UUCP> dg@lakart.UUCP (David Goodenough) writes: >So the bottom line is all you need is the ability to capture the state >of a bit, and set it no matter what, all in one atomic instruction. The key is that it be atomic; not all "add with carry" instructions are. On the PDP-11, we used to use something like TST and INCB as the two semaphore basic instructions; it was tricky due to the bus supporting both byte and word transfers. When generalizing to multiprocessor architectures, many designers seem to have found "test and set" more suitable for the purposes of basic synchronization than an arithmetic operation would be.