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From: olorin@walt.cc.utexas.edu (Dave Weinstein)
Newsgroups: comp.lang.forth
Subject: Re: Cost of Forth Chips
Summary: Pipelining, just say NO!
Message-ID: <17173@ut-emx.UUCP>
Date: 16 Aug 89 13:52:24 GMT
References: <893@mtk.UUCP>
Sender: news@ut-emx.UUCP
Reply-To: olorin@walt.cc.utexas.edu (Dave Weinstein)
Distribution: usa
Organization: The University of Texas at Austin, Austin, Texas
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In article <893@mtk.UUCP> marmar@mtk.UUCP (Mark Martino) writes:
>[...] Brian concludes that in order to operate at clock rates greater
>than the current 10-12 MHZ, Forth chips will have to fall back to using
>pipelining as do RISC chips.

	NO!!! Bearing in mind that the designed use for most of these Forth
chips is in Realtime applications, adding pipelines is one of the worst 
things you can do! Realtime applications need to be predictable (i.e. take
the same number of cycles to do the same thing each time), and throwing in
pipelines destroys that predictability (you get greater *overall* throughput
but actual mileage may vary). I don't believe Harris will do this (they have
been touting the predictability of the RTX family throughout their literature.

--Dave


--
Dave Weinstein			olorin@walt.cc.utexas.edu
(512) 339-4407 Home        	GEnie: DHWEINSTEIN
My employers never agree with me anyway.