Path: utzoo!utgpu!watmath!att!pacbell!ames!lll-winken!tekbspa!optilink!jones From: jones@optilink.UUCP (Marvin Jones) Newsgroups: sci.electronics Subject: Re: Xilinx Summary: Xilinx Reset Problems Message-ID: <2045@optilink.UUCP> Date: 8 Aug 89 18:19:54 GMT References: <8897@june.cs.washington.edu> <3297@tekfdi.FDI.TEK.COM> Organization: Optilink Corporation, Petaluma, CA Lines: 19 We are using a LOT of Xilinx parts in our new product. Among other things, there are major problems with several of the mask sets regarding reset operation. We have had to add 10 gates or so around ALL versions of the parts in order to adequately control the reset timing going to both the Xilinx arrays as well as the 1736 serial configuration PROMs. We have also seen process variations between various runs of the arrays which can cause lockups during the power up initialization phase when using a master / slave serial configuration loading scheme. This requires an additional gate between the Init lead of the slave and the Reset lead of the master. Yes, they are clever parts. Very versatile and fast for prototype development. But lately we are working harder on generating "real" custom VLSI to avoid an ever growing number of Xilinx "surprises" we are finding. I have not been that deeply involved with the problem resolution, but can provide more information if desired.