Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!ucbvax!ucsfcgl!pixar!mccoy
From: mccoy@pixar.UUCP (Daniel McCoy)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <6366@pixar.UUCP>
Date: 16 Aug 89 20:05:03 GMT
References: <828@eutrc3.urc.tue.nl> <26667@amdcad.AMD.COM> <0YrsEMy00V4GQ=CJZw@andrew.cmu.edu> <26676@amdcad.AMD.COM>
Reply-To: mccoy@pixar.UUCP (Daniel McCoy)
Organization: Pixar -- Marin County, California
Lines: 25

In article <26676@amdcad.AMD.COM> tim@amd.com (Tim Olson) writes:
> (Response to other articles about branch shadow restrictions.)
>
>  Does anyone else know of other processors with such restrictions?

Weitek XL.
I left the manuals at my previous job, but, if I remember correctly,
some instruction types make other uses of the field required to control 
neutralization (their term for non-execution of shadow instructions).
Their neutralization control allows shadow instructions to be:
     always executed
     executed only if branch taken
     executed only if branch not taken
     executed and return address incremented for calls
They provide a post-processor for compiled code that does a good job
of filling slots.
In hand coding I was able to fill nearly all of the slots.
The control over execution for branch taken/not taken is especially
good for hand coding.  You can execute the instructions on the
most critical path and put the delays on the least critical paths.

Not a bad processor for embedded controller stuff.
The floating point pipeline is certainly easier to use than the i860.

Dan McCoy	Pixar