Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!gem.mps.ohio-state.edu!ginosko!rex!ukma!rutgers!dptg!ulysses!andante!alice!jmk From: jmk@alice.UUCP Newsgroups: comp.sys.mips Subject: Clearing Intr5* on M/120 Message-ID: <9783@alice.UUCP> Date: 16 Aug 89 03:37:42 GMT Organization: AT&T Bell Laboratories, Murray Hill NJ Lines: 18 The M/120 RISComputer Technical Reference of July 1988 states on page 3-7 Level 5 interrupt (Intr5*)... This interrupt is reset when the interrupt handler reads the contents of the Fault Address Register, ... Whereas, on page 3-11 we find The captured fault address is held until software reads the Interrupt Status Register (ISR). Reading the ISR causes the Intr5* signal to be de-asserted... Which is correct? Jim McKie research!jmk -or- jmk@research.att.com Bell Laboratories