Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!stat!stat.fsu.edu!mccalpin
From: mccalpin@masig3.ocean.fsu.edu (John D. McCalpin)
Newsgroups: comp.arch
Subject: Re: cache speed
Message-ID: 
Date: 18 Aug 89 09:41:10 GMT
References: <1473@unocss.UUCP> <3941@phri.UUCP> <1736@crdgw1.crd.ge.com>
Sender: news@stat.fsu.edu
Organization: Supercomputer Computations Research Institute
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In-reply-to: oconnordm@CRD.GE.COM's message of 18 Aug 89 04:23:41 GMT

In article <1736@crdgw1.crd.ge.com>, Dennis O'Connor writes:
>Summary : it's currently impossible to build a 16-megabyte NMOS,
>CMOS, or TTL memory system with a 25ns access time. But with a good
>cache design, you can build a system with almost the same performance.

Well, it is not exactly 25ns, but each of the 4 cpu's of our ETA-10G
at FSU has 32MBytes of 30ns CMOS SRAM.  The time required for a load
is about 6 cycles, at 7ns/cycle.  Deleting the instruction issue time
(1-2 cycles?), this is getting awfully close to 30ns.
They never could get the 128MByte memory arrays working at 7ns....

--
John D. McCalpin - mccalpin@masig1.ocean.fsu.edu - mccalpin@nu.cs.fsu.edu
		   mccalpin@delocn.udel.edu