Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!ukma!rutgers!bellcore!faline!hammond
From: hammond@faline.bellcore.com (Rich A. Hammond)
Newsgroups: comp.arch
Subject: Re: Content Addressible Memories
Message-ID: <2118@faline.bellcore.com>
Date: 9 Dec 88 14:41:53 GMT
References: <12371@srcsip.UUCP>
Reply-To: hammond@faline.UUCP (Rich A. Hammond)
Organization: Bellcore MRE
Lines: 19

The reason that content addressable memories haven't caught on is
rather simple.  From an IC manufacturing view, there is no "one size
fits all" version to make.  To get reasonable performance one
needs to have the entire word width on a chip, one can't make Nx1 chips
and stack them up to the required word width.  This gives severe
I/O problems for interesting (48 bits and more) size words, either
it takes chips with lots of pins (read lots of $$) or you multiplex I/O
and performance falls down to the level of a RISC processor with cache,
which means you also lost the sale.

Appendix:  Why can't you have x1 chips?  Because you need to know that
the whole word matched, matches of portions of the word aren't enough.
So, an Nx1 chip would need roughly log (base 2) of N pins to communicate
with the other chips and could take multiple cycles to arrive at a
match/no match decision.  Reducing the time to match/no match appears to
require increasing the number of pins.  And these communication pins
have to have pretty hefty drivers on them.

Rich Hammond