Path: utzoo!attcan!uunet!mcvax!ukc!strath-cs!glasgow!icdoc!qmc-cs!harlqn!andrew From: andrew@jung.harlqn.uucp (Andrew Watson) Newsgroups: comp.arch Subject: Re: OISC was Re: ZISC computers Message-ID:Date: 26 Nov 88 23:25:30 GMT References: <3562@hubcap.UUCP> <579@dms.UUCP> Sender: news@harlqn.UUCP Organization: Harlequin Limited, Cambridge, UK Lines: 30 In-reply-to: albaugh@dms.UUCP's message of 17 Nov 88 21:13:06 GMT In article <579@dms.UUCP> albaugh@dms.UUCP (Mike Albaugh) writes: One possible implementation is a machine which has the instruction: Reverse Subtract and skip on Borrow. That is, every instruction has no opcode but does have an address. The accumulator is subtracted from that address and the result left both there and in the accumulator. If the subtraction caused a borrow (i.e. no carry out of the ALU), the subsequent instruction is skipped. The only handwaving required is for the PC to live in a fixed location (say 0, ala PDP-5). A very naive control unit which does one instruction per 6 clock cycles can be implemented, a slightly less naive one can do it in 5 (sometimes 4), and shadowing the PC can get it to 3 (sometimes 2). [ ... lots of interesting detail deleted ... ] I heard that an undergraduate at Manchester University (UK) built something very much like this as a final-year project. He also wrote macros to emulate the 8086 instruction set, and as a result benchmarked his contraption as faster than a stock IBM PC. Would any Manchunians (Mario? Ifor?) like to comment? -- Regards, Andrew. +-----------------------------------------------------------------------------+ | Andrew Watson, Harlequin Limited, andrew@uk.co.harlqn | | Barrington Hall, Barrington, Tel: +44 223 872522 | | Cambridge CB2 5RG, UK Fax: +44 223 872519 | +-----------------------------------------------------------------------------+