Path: utzoo!utgpu!watmath!clyde!att!rutgers!ucsd!sdcsvax!ucsdhub!esosun!seismo!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: Assembly or ....
Message-ID: <1842@scolex>
Date: 3 Dec 88 21:18:51 GMT
References: <1388@aucs.UUCP| <729@convex.UUCP> <1961@crete.cs.glasgow.ac.uk> <7740@boring.cwi.nl> <1039@l.cc.purdue.edu> <79744@sun.uucp>
Reply-To: seanf@sco.COM (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 22

In article <1039@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes:
>
>Can division be pipelined?  In scalar mode on the CYBER 205, division is not
>subject for pipelining.  I believe that this is the case because too much of
>the dividend must be retained throughout.

I don't know how well it can do it theoretically, but I do know that, on a
Cyber 170/760, multiplication is pipelined so that it can be doing a maximum
of three mults (first step, intermediate steps, last step).  Note that the
bottleneck (on a five-cycle instruction, wow) is in the intermediate steps.
This is why you try to multiply using registers that are otherwise unused at
the time 8-).

Division, on the other hand, is *not* pipelined.  You can only do one
division at a time (why he didn't put in more than one division unit is
something I still don't understand), and it takes a *long* time (70 or more
cycles).

-- 
Sean Eric Fagan  | "Engineering without management is *ART*"
seanf@sco.UUCP   |     Jeff Johnson (jeffj@sco)
(408) 458-1422   | Any opinions expressed are my own, not my employers'.