Xref: utzoo comp.compilers:360 comp.arch:7341 Path: utzoo!attcan!uunet!husc6!spdcc!ima!compilers-sender From: davis@clocs.cs.unc.edu (Mark Davis) Newsgroups: comp.compilers,comp.arch Subject: Real Compiler for One Instruction Computer? Summary: Has anyone ever seriously investigated this? Keywords: ZISC RISC SB compiler realized Message-ID: <5507@thorin.cs.unc.edu> Date: 23 Nov 88 14:25:19 GMT Sender: compilers-sender@ima.ima.isc.com Reply-To: davis@clocs.cs.unc.edu (Mark Davis) Lines: 20 Approved: compilers@ima.UUCP Recently on comp.arch there has been discussion of a zero instruction set computer (ZISC) which actually is a one operation computer. One architecture is the Subtract and branch on less that zero instruction with 3 or 4 operands (I find some references to Van der Poel, 1956 for this construction). Has anyone ever tried to write a compiler for such a machine or done any significant simulations? Thanks - Mark [I've heard that in the 1950's there was a Ph.D. thesis implementing a Fortran compiler for a Turing machine, which is sort of the same spirit. but would be fascinated to hear of any other work in that vein. I suspect it would be filed under theory of computation. -John] [From davis@clocs.cs.unc.edu (Mark Davis)] -- Send compilers articles to ima!compilers or, in a pinch, to Levine@YALE.EDU Plausible paths are { decvax | harvard | yale | bbn}!ima Please send responses to the originator of the message -- I cannot forward mail accidentally sent back to compilers. Meta-mail to ima!compilers-request