Xref: utzoo comp.lsi:604 comp.lsi.cad:59 Path: utzoo!utgpu!watmath!clyde!att!rutgers!mailrus!ames!elroy!orion.cf.uci.edu!paris.ics.uci.edu!venera.isi.edu!sllu From: sllu@venera.isi.edu (Shih-Lien Lu) Newsgroups: comp.lsi,comp.lsi.cad Subject: enhancement to magic/ext2sim/sim2spice Keywords: Berkeley VLSI tools, extraction, transistors, source and drain area Message-ID: <6910@venera.isi.edu> Date: 30 Nov 88 00:45:58 GMT Organization: USC-Information Sciences Institute Lines: 14 Berkeley tool/Magic users; I have done some patching work to magic_extraction ext2sim and sim2spice, so that the area and perimeter of the transistor source and drain will be automatically extracted instead of a lumped capacitance. Using source/drain area and perimeter with the SPICE MODEL deck supplied by MOSIS to do SPICE simulation will give more accurate results. To obtain the modification, FTP to vlsi-cad.isi.edu with "anonymous" as the login_id and "ident" as the password. Get the file "mag_ext_sim.ar". This is an archived file. To restore individual files type "ar x mag_ext_sim.ar". Shih-Lien Lu sllu@mosis.edu