Xref: utzoo comp.arch:7438 comp.unix.questions:10473
Path: utzoo!utgpu!watmath!clyde!att!rutgers!mailrus!ames!amdcad!crackle!tim
From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch,comp.unix.questions
Subject: Re: 88K table walk
Message-ID: <23673@amdcad.AMD.COM>
Date: 3 Dec 88 00:56:11 GMT
References: <415@ncr-sd.SanDiego.NCR.COM> <1583@nud.UUCP>
Sender: news@amdcad.AMD.COM
Reply-To: tim@crackle.amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
Lines: 18
Summary:
Expires:
Sender:
Followup-To:

In article <1583@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes:
| In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes:
| >According to Motorola, the 88200 CMMU does not cache the page and
| >segment descriptors it fetches during a table walk. This would seem
| 
|     Wrong! The 88200 does cache page descriptors.  Up to 56 page descriptors
| (each descriptor maps 4K of virtual space) can be cached in each CMMU.  The
| page descriptor cache is managed by the CMMU.

Yes, the translation is cached in the TLB entries, but I think the
question was do the memory accesses that are performed during the table
walk also get cached in the data cache? Or must they always go to main
memory? 


	-- Tim Olson
	Advanced Micro Devices
	(tim@crackle.amd.com)