Path: utzoo!utgpu!watmath!clyde!att!rutgers!gatech!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!munnari!otc!metro!ipso!stcns3!stca77!peter From: peter@stca77.stc.oz (Peter Jeremy) Newsgroups: comp.arch Subject: Re: Assembly or .... (two-result functions) Summary: down with implied addressing Message-ID: <373@stca77.stc.oz> Date: 7 Dec 88 02:30:38 GMT References: <1047@l.cc.purdue.edu> Reply-To: peter@stca77.stc.oz (Peter Jeremy) Organization: Alcatel-STC, Alexandria, AUSTRALIA Lines: 20 In article <1047@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes: [ 80387 FSINCOS instruction returns results in ST(0) and ST(1) ] >This being comp.arch, I must also state that I consider it unfortunate that >this type of operation requires that specific registers must be used; in other >situations, this is certainly considered a bad thing. This instruction is typical of Intel processors - they all have highly non- orthogonal instruction sets, with specialised instructions containing implicit register references. Intel promote this as "a good thing" and have register names to indicate their uses. Intel processors in general are a real pain to use. Even when you go to the 80386 and finally escape from the 64k limit, you still can't nest loops, or use loops with shifts or string instructions without shuffling registers. (Not to mention having to remember all the side effects whilst writing code). -- Peter Jeremy (VK2PJ) peter@stca77.stc.oz Alcatel-STC Australia ...!uunet!stca77.stc.oz!peter 41 Mandible St peter%stca77.stc.oz@uunet.UU.NET ALEXANDRIA NSW 2015