Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!mit-eddie!uw-beaver!cornell!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!dpm From: dpm@k.gp.cs.cmu.edu (David Maynard) Newsgroups: comp.arch Subject: Re: 88K table walk Message-ID: <3798@pt.cs.cmu.edu> Date: 6 Dec 88 18:48:19 GMT Reply-To: dpm@k.gp.cs.cmu.edu (David Maynard) Organization: Carnegie-Mellon University, CS/RI Lines: 38 Keywords: > I'm asking if the data from the two fetches done during the table walk are > placed in the d/i cache. If not, why not? I was just thinking about asking this question on a final exam in a computer architecture course. (Then I decided it was too hard.) I don't know why Motorola did one thing or another, but here are my 2 cents worth. The way I read the initial data sheet it doesn't look like the 88200 caches address translation tables if you access them during a table walk. However, if the PATC/BATC are big enough, you might just be polluting the cache if you loaded the table entries. Presumably, the only way a "normal" user program will access the tables is via a table walk. If you cache the results of the walk in the PATC then you supposedly won't need to access the table locations again for some time. Also, with 4K pages and a 16K cache, you can cycle a lot of data through the cache without having to do many more address translations. It is possible that the table entries would usually be flushed from the cache before they were used again. It seems that there might be more of an argument for cacheing the 1st-level tables ("segment" tables) since you might be touching several pages in the same segment and might benefit by being able to speed up the address translation for those nearby pages. The OS will actually be working with the tables as data. I assume that data accesses would load the table entries into the D-cache. There might be a case (page faults maybe) where already having a particular table entry already cached from a walk might speed up an OS function. I'll have to think about that one.... --- David P. Maynard (dpm@cs.cmu.edu) Dept. of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 --- Any opinions expressed are mine only. I haven't asked the ECE department or CMU what they think. --- --