Xref: utzoo comp.arch:7435 comp.unix.questions:10466 Path: utzoo!utgpu!watmath!clyde!att!rutgers!mailrus!ncar!noao!asuvax!nud!tom From: tom@nud.UUCP (Tom Armistead) Newsgroups: comp.arch,comp.unix.questions Subject: Re: 88K table walk Message-ID: <1583@nud.UUCP> Date: 2 Dec 88 20:17:47 GMT References: <415@ncr-sd.SanDiego.NCR.COM> Reply-To: tom@nud.UUCP (Tom Armistead) Organization: Motorola Microcomputer Division, Tempe, Az. Lines: 12 In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >According to Motorola, the 88200 CMMU does not cache the page and >segment descriptors it fetches during a table walk. This would seem Wrong! The 88200 does cache page descriptors. Up to 56 page descriptors (each descriptor maps 4K of virtual space) can be cached in each CMMU. The page descriptor cache is managed by the CMMU. In addition, per CMMU, software can map up to eight 512K chunks of memory via the block address translation cache and avoid table walks on contiguous areas of memory (e.g. kernel text and data, i/o areas, etc.). --