Xref: utzoo comp.arch:7423 comp.unix.questions:10451
Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!ucsd!ncr-sd!ivory!jml
From: jml@ivory.SanDiego.NCR.COM (Michael Lodman)
Newsgroups: comp.arch,comp.unix.questions
Subject: 88K table walk
Message-ID: <415@ncr-sd.SanDiego.NCR.COM>
Date: 2 Dec 88 16:53:34 GMT
Sender: news@ncr-sd.SanDiego.NCR.COM
Reply-To: jml@ivory.SanDiego.NCR.COM (Michael Lodman)
Organization: NCR Corporation - Advanced Development
Lines: 12

According to Motorola, the 88200 CMMU does not cache the page and
segment descriptors it fetches during a table walk. This would seem
to me to have a negative impact on performance. Is this standard
practise for table walks, and if not why did Motorola do it that way?
John Mashey, perhaps you could tell me if MIPS does this.

Michael Lodman  (619) 485-3335
Advanced Development NCR Corporation E&M San Diego
mike.lodman@ivory.SanDiego.NCR.COM 
{sdcsvax,cbatt,dcdwest,nosc.ARPA}!ncr-sd!ivory!jml

When you die, if you've been very, very good, you'll go to ... Montana.