Path: utzoo!utgpu!water!watmath!clyde!att!rutgers!mit-eddie!ll-xn!ames!lll-tis!lll-winken!maddog!brooks
From: brooks@maddog.llnl.gov (Eugene Brooks)
Newsgroups: comp.arch
Subject: Re: Software Distribution
Message-ID: <12602@lll-winken.llnl.gov>
Date: 27 Sep 88 00:18:53 GMT
References: <5655@june.cs.washington.edu> <340@istop.ist.CO.UK> <15440@ames.arc.nasa.gov> <944@l.cc.purdue.edu>
Sender: usenet@lll-winken.llnl.gov
Reply-To: brooks@maddog.UUCP (Eugene Brooks)
Organization: Lawrence Livermore National Laboratory
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In article <944@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes:
>I agree that vector microprocessors will be fairly cheap.  But which type of
>architecture?  I am familiar with several of them.  I have used the CYBER 205,
>and it has useful instructions which are not vectorizable at all, or vectoriz-
>able only with difficulty and at considerable cost, on vector register
>machines.  Or will we be using massive parallelism?  Try procedures which
Just what instructions are we talking about here?  Lets pick an alternative
to compare to, say the CRAY XMP 48 instruction set.