Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!cornell!uw-beaver!tektronix!reed!kamath From: kamath@reed.UUCP (Sean Kamath) Newsgroups: comp.sys.apple Subject: Re: Zip Chip Question. Message-ID: <10386@reed.UUCP> Date: 21 Sep 88 01:23:52 GMT References:Reply-To: kamath@reed.UUCP (Sean Kamath) Organization: Reed College, Portland OR Lines: 54 In article tmetro@lynx.northeastern.EDU writes: >No. The No-Slot-Clock (manufactured by Dallas Semiconductor - dst. by >SMT) has its own internal frequency reference. Besides the Zip Chip's >method of acceleration does not affect the system clock or speed external >to the CPU. True enough, but, as stated previously, if it happens to cache in the wrong place, it will destroy the "wakeup" sequnce on the a0 line. (or is it the a4 line?) >Be warned that the No-Slot-Clock may not work with the Zip Chip for other >(yet unknown) reasons. I have a No-Slot-Clock installed in my //c which >does not opperate when I have a W65C802 CPU installed in place of the 65C02. >Western design Center (creator of the 65C802/816) is looking into the >problem. Yes, I had the same problem. I don't think it is "anyone's" fault. By that I mean I talked to SMT (Who at the time had just hired a mr. Sanders of "Understanding the Apple . . ." fame.) and they had not a clue as to what was wrong. Timing chart *are* just a bit off, but: It works just fine in micro #2 with a 65802 in it. Soooooo... I think it's your MMU. "Huh?" he grunts. I have looked and looked, but nowhere have I found documentation on it: Appearantly (Dennis Domms told me this at the last applefest), a few of the MMU's in the //e's were a little screwy. They could cause timing errors. Since the MMU is directly responsible for handling the R\W line, this *might* be the problem. Since I can't get any docs on this "bug", all I can say is: Try another MMU. Maybe it'll work. If it *does*, then PLEASE send me the stuff (i.e. part number and all that) for the chip, we can compare it to mine, and issue a "warning" about this. > Tom Metro Sean Kamath PS I'm Back! PPS And I'm on BITNET! Weeeeee -- UUCP: {decvax allegra ucbcad ucbvax hplabs ihnp4}!tektronix!reed!kamath CSNET: reed!kamath@Tektronix.CSNET || BITNET: kamath@reed.BITNET ARPA: reed!kamath@PSUVAX1.CS.PSU.EDU US Snail: 3934 SE Boise, Portland, OR 97202-3126 (I hate 4 line .sigs!)