Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!oliveb!ames!ncar!cruff From: cruff@ncar.ucar.edu (Craig Ruff) Newsgroups: comp.arch Subject: Re: Help: Thrashing on TLB input? Keywords: TLB, cache, mapping, hashing, collision, thrashing Message-ID: <734@ncar.ucar.edu> Date: 21 Sep 88 16:58:34 GMT References: <3907@psuvax1.cs.psu.edu> <22876@amdcad.AMD.COM> <16891@apple.Apple.COM> <16102@shemp.CS.UCLA.EDU> Reply-To: cruff@handies.UCAR.EDU (Craig Ruff) Organization: Scientific Computing Division/NCAR, Boulder CO Lines: 18 In article <16102@shemp.CS.UCLA.EDU> casey@cs.ucla.edu (Casey Leedom) writes: > The problem turned out to be that the Sun 3/2XX cache was 64Kb with 16 >byte lines indexed by a formula very dependent on the LSBs of the >address. ... > > We finally got Sun 3/1XX performance by offsetting the source and >destination arrays by 24 bytes. ... This is discussed in a Sun Sales Tactical Engineering note titled: The Sun 3/200 and Sun 4/200 Cache Ask your Sun rep to get you a copy. It discusses the way the cache works and performance issues like that above. -- Craig Ruff NCAR INTERNET: cruff@ncar.UCAR.EDU (303) 497-1211 P.O. Box 3000 CSNET: cruff@ncar.CSNET Boulder, CO 80307 UUCP: cruff@ncar.UUCP