Path: utzoo!attcan!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com
Newsgroups: comp.arch
Subject: Re: Transputer based systems.
Message-ID: <9378@cup.portal.com>
Date: 23 Sep 88 18:34:59 GMT
References: <253@uceng.UC.EDU> <3011@hubcap.UUCP> <69514@sun.uucp>
Organization: The Portal System (TM)
Lines: 25
XPortal-User-Id: 1.1001.5156

>These are the NSIEVE (Sieve Of Eratosthenes) results I have at this time.
 
> (3) AMD 29000 at 25 MHz.  Branch Target Cache (BTC) was ON.  Metaware 
>     High C 29000 V2.1 with -O option. No effective memory wait states.
>     Memory was all physical (i.e., No cacheing).
>     From Trevor Marshall, BIX 'supermicros/bench #925', 07 Sep 1988.

Well, "no effective memory wait states" is kinda misleading.  The data
memory access time for this board is two clock cycles; now, maybe this
latency is always overlapped in this benchmark, thus prompting the
comment "no effective memory wait states," but that doesn't change the
implementation details!  Also, the instruction memory has zero wait
states (I *HATE* this damn term, but we're stuck with it) most of the
time, but it can have anywhere from 1 cycle (zero "wait states"; see
why I hate this term?) to 5 cycle latency, depending on circumstances
surrounding branches and static column alignment, page boundaries, etc.

The point I am trying to make is that the McCray board is neither a
"hot box" nor a system with caches.  The 29000 would do better on this
benchmark if it had the advantage of caches like those of the other
systems.  (Note that the current implementation of the 29000 has a
bug:  the BTC doesn't always work right.  This is the reason for the
inclusion of two 29000 times in the NISEVE stats.)

What is the number for the 25 MHz R3000 box?  Is it close to the Amdahl?