Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!uflorida!novavax!hcx1!ldh From: ldh@hcx1.SSD.HARRIS.COM Newsgroups: comp.sys.ibm.pc Subject: Re: RAM speed per clock rate Message-ID: <47200009@hcx1> Date: 11 Aug 88 22:03:00 GMT References: <3075@tekig4.TEK.COM> Lines: 14 Nf-ID: #R:tekig4.TEK.COM:3075:hcx1:47200009:000:710 Nf-From: hcx1.SSD.HARRIS.COM!ldh Aug 11 18:03:00 1988 >/* Written 10:24 am Aug 9, 1988 by bobmon@iuvax.UUCP in hcx1:comp.sys.ibm.pc */ >Okay, I've seen some interesting RAM-timing information flow past, and I >understand what a wait state does, but I have one simple question: what >IS a wait state? Is it a CPU clock cycle? Is it some portion of a clock >cycle related to the memory-chip timing (what relationship?)? Does it >come from some mysterious secret delay line somewhere? What??? >-- >-- bob,mon (bobmon@iuvax.cs.indiana.edu) >-- "Aristotle was not Belgian..." - Wanda "Wait states" are cycles of the system clock that the CPU, or other DMA device, has to waste (wait) before obtaining the desired results from the memory being accessed.