Path: utzoo!attcan!uunet!husc6!rutgers!ucsd!ames!amdcad!phil From: phil@amdcad.AMD.COM (Phil Ngai) Newsgroups: comp.arch Subject: Re: Dynamic RAM internals Message-ID: <22597@amdcad.AMD.COM> Date: 11 Aug 88 00:57:55 GMT References: <1988Aug8.163944.29383@utzoo.uucp> <11815@steinmetz.ge.com> Reply-To: phil@amdcad.UUCP (Phil Ngai) Organization: Advanced Micro Devices Lines: 21 In article <11815@steinmetz.ge.com> oconnor%sungod@steinmetz.UUCP writes: >( Now, Video DRAMs do >contain a shift register for shifting out a selected word, >but it is NOT the primary data storage mechanism. So I digress. ) Actually, there are many video DRAMs which implement the so called shift register as a little piece of fast static RAM addressed by a counter. How fast? A Toshibia megabit VRAM accesses in 25 nS. Part of that is the counter working so the RAM itself must be maybe 15-20 nS. With regard to the question of how DRAMs work, Mr Ward is so wrong I can't believe it. But I wonder how the new-fangled "DRAMS" with static column access or extended page mode work. Do they actually discharge the capacitor and write it back with each page access? In 50 nS? -- I speak for myself, not the company. Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or phil@amd.com