Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!pasteur!ucbvax!decwrl!hplabs!hpl-opus!hpccc!hp-sde!hpfcdc!hpislx!hplvla!hplvly!boyne
From: boyne@hplvly.HP.COM (Art Boyne)
Newsgroups: comp.sys.ibm.pc
Subject: Re: cycle time vs. access time (was: RAM speed per clock rate)
Message-ID: <4420009@hplvly.HP.COM>
Date: 10 Aug 88 16:45:29 GMT
References: <9703@dartvax.Dartmouth.EDU>
Organization: HP Loveland Inst Div, CO
Lines: 31

bobmon@iuvax.cs.indiana.edu (RAMontante) writes:

> I understand what a wait state does, but I have one simple question:  what
> IS a wait state?  Is it a CPU clock cycle?  Is it some portion of a clock
> cycle related to the memory-chip timing (what relationship?)?  Does it
> come from some mysterious secret delay line somewhere?  What???

When the 80x86 and 680x0 CPU chips access memory, they set up address (and
if a write, data), then issue a start-memory-cycle indication (/S0 & /S1 on
the 80286, /AS on the 680x0).  The processor then waits for a memory complete
indication from the rest of the hardware (READY on the 80x86, DTACK on the
680x0).  Most systems are designed with a fixed time between the start flag
and the complete handshake.  Typically, either a shift register whose input
is the start flag or a counter enabled by the start flag is used, with a
predetermined shift bit/count generating the complete handshake.  Meanwhile
the CPU is in "waiting" state or condition (ie, doing NOTHING).  Now, with
fast memory, the access can be completed in 1 clock cycle.  With slower memory,
more than one clock cycle's worth of time is needed, and a different shift
bit/count is used.  This results in an delay which is an integral number of
clock cycles.  So, a wait state is: 1) one state in the state transition
diagram of the CPU where the CPU does nothing, and 2) one clock cycle's worth of
delay dictated by the slow memory.

This description explains why simply changing the clock frequency of a CPU
chip to speed up a system is very dangerous.  The system waits the same number
of (now shorter) clock cycles for every access, so each access is now faster.
But unless the RAM chips involved support the faster accesses, disaster is
only a few nano-seconds away!

Hope this helps.

Art Boyne,  !hplabs!hplvly!boyne