Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!ucsd!ucsdhub!hp-sdd!hplabs!hp-pcd!hpcvca!scott
From: scott@hpcvca.HP.COM (Scott Linn)
Newsgroups: comp.arch
Subject: Re: History of personal computing (LONG)
Message-ID: <5670002@hpcvca.HP.COM>
Date: 10 Aug 88 17:39:27 GMT
References: <5946@venera.isi.edu>
Organization: Hewlett-Packard Co., Corvallis, Oregon
Lines: 34

/ hpcvca:comp.arch / ward@cfa.harvard.EDU (Steve Ward) /  3:41 pm  Aug  9, 1988 /

>Dynamic RAM does not have destructive readout.  In fact, the DRAM is
>refreshed with a read-only cycle in typical applications.  DRAM's do
>have special timing and refresh considerations, though.

True.
				   
>A DRAM is made up of one or more circular, dynamic shift registers with
 >read/write/address logic.  As the bits circulate through the shift
>registers, the data decays.  This is because the shift registers are
>analog and the data are electrical charges.  This means that
>periodically the charges must be reamplified.  The act of reading a
>DRAM will cause this reamplification, as will other methods (RAS-only
			>access, for example).


>

>fire away
----------

				   
DRAMS do refresh on read, but are not circular shift register arrays.
Data is stored on a capacitor in a regular memory array (like a static
ram), and the data eventually leaks off if not restored.  The data is
restored on read via a sense amp latch which feeds back to the memory
cell and restores the correct level.

I believe bubble memories consist of circular shift registers...


Scott Linn
HP - Northwest IC Division