Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: memories and destructive readout
Message-ID: <1988Aug10.205531.24041@utzoo.uucp>
Organization: U of Toronto Zoology
References: <5946@venera.isi.edu> <46500024@uxe.cso.uiuc.edu> <1988Aug8.163944.29383@utzoo.uucp> <1075@cfa.cfa.harvard.EDU>
Date: Wed, 10 Aug 88 20:55:31 GMT

In article <1075@cfa.cfa.harvard.EDU> ward@cfa.harvard.EDU (Steve Ward) writes:
>Dynamic RAM does not have destructive readout.  In fact, the DRAM is
>refreshed with a read-only cycle in typical applications...

True on the external level, but the *chip* is doing a destructive read and
write-back:  the only way to read the charge on the storage capacitors
in a DRAM is to pull it out and then see if anything came.  Normally
the sense amplifiers then immediately put it back.  This is why doing a
read does a refresh also.

>A DRAM is made up of one or more circular, dynamic shift registers with
>read/write/address logic.  As the bits circulate...

Are you sure you aren't confusing DRAMs with the old CCD memories?  There
are no shift registers in DRAMs (ignoring video RAMs!) that I know of.
-- 
Intel CPUs are not defective,  |     Henry Spencer at U of Toronto Zoology
they just act that way.        | uunet!attcan!utzoo!henry henry@zoo.toronto.edu