Path: utzoo!utgpu!attcan!uunet!husc6!mailrus!uwmcsd1!ig!agate!saturn!ucscb.UCSC.EDU!spcecdt From: spcecdt@ucscb.UCSC.EDU (Space Cadet) Newsgroups: comp.arch Subject: Regarding shift-register-like memories Message-ID: <4473@saturn.ucsc.edu> Date: 11 Aug 88 04:08:42 GMT Sender: usenet@saturn.ucsc.edu Reply-To: spcecdt@ucscb.UCSC.EDU (Space Cadet) Distribution: na Organization: University of California, Santa Cruz; CATS Lines: 8 I recall reading some time ago about a project that Clive Sinclair was working on to make "solid-state disks" using wafer scale integration. The idea was to use some shift-register like scheme connecting the memory arrays on the wafer so that defective arrays could be bypassed. Does anyone know if this is still being worked on? -- > John H. DuBois III # spcecdt@ucscb.ucsc.EDU ...!ucbvax!ucscc!ucscb!spcecdt <