Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!cornell!uw-beaver!teknowledge-vaxc!sri-unix!ctnews!starfish!cdold
From: cdold@starfish.Convergent.COM (Clarence Dold)
Newsgroups: comp.sys.ibm.pc
Subject: Re: RAM speed per clock rate
Message-ID: <626@starfish.Convergent.COM>
Date: 9 Aug 88 23:57:58 GMT
References: <11431@iuvax.cs.indiana.edu>
Organization: Convergent Technologies, San Jose, CA
Lines: 16

From article <11431@iuvax.cs.indiana.edu>, by bobmon@iuvax.cs.indiana.edu (RAMontante):
> Okay, I've seen some interesting RAM-timing information flow past, and I
> understand what a wait state does, but I have one simple question:  what
> IS a wait state?  Is it a CPU clock cycle?  Is it some portion of a clock
> cycle related to the memory-chip timing (what relationship?)?  Does it
> come from some mysterious secret delay line somewhere?  What???

A wait state is inserted by timing machinery separate from the CPU chip or the 
RAM itself.  When the system is designed, a particular speed of RAM is chosen.
Timing circuits are built around those chips.  If the economies, or whatever,
cause this calculated time to be slower than the minimum time where the CPU
could take it, the excess timing is called 'Wait States'.  It might be 
jumper selectable, so that the user could pay more for faster chips, and
eliminate the wait states, but it is independent of the RAM installed.
There is no actual handshake coming back from the RAM, the handshake that
the CPU sees is generated by some timing circuitry.