Path: utzoo!utgpu!attcan!uunet!husc6!bloom-beacon!oberon!cit-vax!mangler From: mangler@cit-vax.Caltech.Edu (Don Speck) Newsgroups: comp.arch Subject: Re: Dynamic RAMs (WAS: History of personal computing (LONG) ) Summary: History and principles of operation Message-ID: <7576@cit-vax.Caltech.Edu> Date: 11 Aug 88 09:34:30 GMT References: <5946@venera.isi.edu> <46500024@uxe.cso.uiuc.edu> <5460@june.cs.washington.edu> Organization: California Institute of Technology Lines: 59 In article <5460@june.cs.washington.edu>, pardo@june.cs.washington.edu (David Keppel) writes: > Each capacitor is tied to the gate of a transistor, so that when you > put current in the collector, current will come out the emitter if and > only if the capacitor was charged. In the actual construction of the > DRAM, the capacitor is actually part of the transistor. Although I think that Fairchild actually made a 4K dRAM in I^2 L (Integrated Injection Logic) in the late 1970's, bipolar transistors make leaky switches. MOSFETS are the rule, and the capacitor is a MOS capacitor. MOSFETS isolate so well that the dominant leakage is through parasitic reverse-biased diodes, not the transistors. The first dRAM, the Intel 1103 (1K bits) circa 1971, used one MOSFET to place charge onto the gate of an output transistor, and a third transistor for read select. Writing was 32 bits at a time; to write one bit was a read-modify-write affair, like magnetic core. The 3-transistor dRAM cell was abandoned when the 1-transistor cell was invented at IBM in the early 1970's, although the Mead & Conway VLSI text in 1978 re-popularized it among academics. It "looks digital" but is actually plagued with analog problems. The 1-transistor cell, used in the 4K through 4M chips, stores charge under the gate of a MOS capacitor (typically with a very thin dielectric) and dumps it onto a bit line. The final state of the bit line will vary by a few tenths of a volt depending on what was stored. Meanwhile, a reference cell sets an identical bit line to an intermediate value. A 2-transistor positive-feedback differential amplifier (its outputs cross-coupled to its inputs) pulls down on whichever input has lower voltage. The amplifier must be powered down while its inputs are being set up, and turned on slowly. Then the higher-voltage input is pulled up, typically with a similar amplifier built with the complementary device. Some of the mid-1970's 4K dRAMs used two capacitors per bit for differential storage, instead of a reference cell. The noise immunity is better, and analysis is markedly easier. The 2-transistor cell can be thought of as a 4-transistor cell with the differential pair shared among many cells. Static RAMs go through the same kind of read regeneration on a cell-by-cell basis that a dRAM does on a column-by-column basis. Writing either a dRAM or sRAM is done by simply overpowering one of the sense amplifiers, forcing the bit lines to the desired value, while the remaining amplifiers perform a normal read/refresh. There is no need for read-modify-write except in the case of chips with builtin ECC. A static-column dRAM leaves the amplifiers fully powered up until RAS is deasserted, so that they can drive the output wires more than once. In article <11815@steinmetz.ge.com> oconnor@nuke.steinmetz (Dennis M. O'Connor) writes: > ( I think on some designs the data is actually > INVERTED when re-written, and one bit per word is kept around to > keep track of wether the bits are in true or complement form. ) This is only advantageous with 3-transistor cells, whose read data is the inverse of what was written. However, half of the cells in a 1-transistor dRAM array read and write inverted data because they connect to the inverting side of the differential sense amplifier. Don Speck speck@vlsi.caltech.edu {amdahl,ames!elroy}!cit-vax!speck