Path: utzoo!attcan!uunet!yale!husc6!cfa!ward From: ward@cfa.harvard.EDU (Steve Ward) Newsgroups: comp.arch Subject: Re: History of personal computing (LONG Summary: not exactly Message-ID: <1075@cfa.cfa.harvard.EDU> Date: 9 Aug 88 22:41:59 GMT References: <5946@venera.isi.edu> <46500024@uxe.cso.uiuc.edu> <1988Aug8.163944.29383@utzoo.uucp> Organization: Harvard-Smithsonian Ctr. for Astrophysics Lines: 55 In article <1988Aug8.163944.29383@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: > In article <46500024@uxe.cso.uiuc.edu> mcdonald@uxe.cso.uiuc.edu writes: > >(for you newcomers, in core memories a read destroyed the contents of the > >cores,so every read had to be followed by a write)... > > Dynamic RAMs are the same way, actually, although many people aren't aware > of this because the chips hide most of the ugly details. It's one of the > reasons why DRAM timing specs are sacrosanct and you take shortcuts at > your peril. (Which means, for example, that if your CPU is in the habit of > starting an access and then changing its mind, you have to be careful that > the DRAM still sees a full legal access of some kind.) > -- > MSDOS is not dead, it just | Henry Spencer at U of Toronto Zoology > smells that way. | uunet!attcan!utzoo!henry henry@zoo.toronto.edu actually, this is not correct. Magnetic cores operated with destructive readout, as claimed. This meant any read had to be coupled with a write-back cycle to retain the information. Dynamic RAM does not have destructive readout. In fact, the DRAM is refreshed with a read-only cycle in typical applications. DRAM's do have special timing and refresh considerations, though. A DRAM is made up of one or more circular, dynamic shift registers with read/write/address logic. As the bits circulate through the shift registers, the data decays. This is because the shift registers are analog and the data are electrical charges. This means that periodically the charges must be reamplified. The act of reading a DRAM will cause this reamplification, as will other methods (RAS-only access, for example). Reading does not destroy the data. The critical timing and special refresh considerations are related to the dynamic shift register nature of storage and access and the requirement to reamplify the shift register charges. I suppose one can construe destruction of a sort, in that in the act of reading, the stored charge feeds an amplifier which amplifies and restores a new charge into the shift register. This is really not a destructive readout, howeveer. The act of reading does not destroy the charge per-se, as it did in the magnetic cores. Certainly there is no DRAM write cycle automatically coupled with every DRAM read cycle, either, and I don't think the reference was to anything but a possible DRAM internal-only event, in any case. The exact internal goings-on are explained only at the block diagram level in data sheets, and this a recap of such an (old) data sheet as I understand it.fire away