Path: utzoo!utgpu!attcan!uunet!steinmetz!nuke!oconnor From: oconnor@nuke.steinmetz (Dennis M. O'Connor) Newsgroups: comp.arch Subject: Dynamic RAM internals Summary: Henry Spencer is, typically, correct. Message-ID: <11815@steinmetz.ge.com> Date: 10 Aug 88 13:07:04 GMT References: <1988Aug8.163944.29383@utzoo.uucp> Sender: news@steinmetz.ge.com Reply-To: oconnor%sungod@steinmetz.UUCP Organization: GE Corporate R&D Center Lines: 46 An article by ward@cfa.harvard.EDU (Steve Ward) says: ] In article <>, henry@utzoo.uucp (Henry Spencer) writes: ] > In article <> mcdonald@uxe.cso.uiuc.edu writes: ] > >... in core memories a read destroyed the contents of the cores, ] > >so every read had to be followed by a write)... ] > ] > Dynamic RAMs are the same way, actually, although many people aren't aware ] > of this because the chips hide most of the ugly details. [...] ] ] actually, this is not correct. actually, Henry Spencer is absolutely correct. Obviously, you weren't aware of it because the chips hide the ugly details. :-) ] Dynamic RAM does not have destructive readout. In fact, the DRAM is ] refreshed with a read-only cycle in typical applications. DRAM's do ] have special timing and refresh considerations, though. A write cycle also refreshes one row of the DRAM array. But changes one of the bits. So writes aren't generally used for refresh-only cycles. :-) ] A DRAM is made up of one or more circular, dynamic shift registers with ] read/write/address logic. [...] This is dead wrong. DRAMs are made up of one or more arrays of one-capacitor-one-transistor cells. On a read ( and before a write, as well ), activating a word line cause one row of these cells to turn on their transistors, dumping their charges, DESTRUCTIVELY, onto the sense lines. Whatever else may happen, this data is later-in-the-cycle written back onto the sense lines, with the word line still active, recharging the caps. ( I think on some designs the data is actually INVERTED when re-written, and one bit per word is kept around to keep track of wether the bits are in true or complement form. ) Now bubble memories ARE shift-register based. That's why they have "average latency" specs. Ya gotta wait for the bit to shift around. ]