Path: utzoo!utgpu!attcan!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!uw-june!pardo From: pardo@june.cs.washington.edu (David Keppel) Newsgroups: comp.arch Subject: Dynamic RAMs (WAS: History of personal computing (LONG) ) Message-ID: <5460@june.cs.washington.edu> Date: 10 Aug 88 16:30:01 GMT References: <5946@venera.isi.edu> <46500024@uxe.cso.uiuc.edu> <1988Aug8.163944.29383@utzoo.uucp> <1075@cfa.cfa.harvard.EDU> Reply-To: pardo@cs.washington.edu (David Keppel) Organization: U of Washington, Computer Science, Seattle Lines: 55 >>mcdonald@uxe.cso.uiuc.edu writes: >>>[ Core has destructive read ] >henry@utzoo.uucp (Henry Spencer) writes: >>[ So do DRAMs ] ward@cfa.harvard.EDU (Steve Ward) writes: >[ No they don't, they're just shift registers ] This flies in the face of what I was told in digital design. If anybody knows differently, please tell me (e-mail) and I'll summarize. Here's what I remember of what I was told: A dynamic RAM is created by making lots of "wells" in the substrate (say, p-type silicon) and filling the wells with another (n-type) silicon. The substrate is, say, grounded, so there is a (small) capacitive effect between the well and the fill. Each capacitor is tied to the gate of a transistor, so that when you put current in the collector, current will come out the emitter if and only if the capacitor was charged. In the actual construction of the DRAM, the capacitor is actually part of the transistor. The DRAM is organized as an array of transistors, say 256 x 256. Each collector is tied to one of 256 "row" wires, so each "row" wire is is connected to 256 transistors. Each collector is tied to one of 256 "column" wires. Each column wire is tied to 256 transistors, and NONE of the transistors on a column wire share a row wire. The row wires are connected to a demultiplexer taking 8 bits in and turning on exactly one of the 256 row wires. Each column wire is connected to an amplifier. The amplifier is unusual, in that at the begining of a read cycle it is initially set to be unstable, niether on nor off, but half-way in-between (e.g., 2.5 volts on a 0/+5v supply). When one of the row wires is turned on, 256 transistors, one on each column-wire, can potentially conduct; those that have their gates connected to charged transistors *do* conduct, and drive the unstable amplifier high. Those that have their gates discharged don't conduct, and a pull-down resistor on the column wire pulls the amplifier low. The only trick in this is that the capacitor, if it was charged initially, has since been discharged as it provided current for the transistor to conduct. The on/off-ness of the particular row has moved out of the capacitors and in to the amplifiers. The amplifiers (which are driving multiplexers and other amplifiers that drive the data lines) *also* drive the column wires. Since the capacitor is actually part of the transistor, the voltage appearing on the column wire will recharge the capacitor. At least that's what mom told me. ;-D on ( Manhattanizing the computer architecture skyline ) Pardo -- pardo@cs.washington.edu {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo