Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!mailrus!husc6!cfa!ward
From: ward@cfa.harvard.EDU (Steve Ward)
Newsgroups: comp.arch
Subject: Re: Dynamic RAMs (WAS: History of personal computing (LONG) )
Summary: zeroing in...
Message-ID: <1078@cfa.cfa.harvard.EDU>
Date: 10 Aug 88 23:30:30 GMT
References: <5946@venera.isi.edu> <46500024@uxe.cso.uiuc.edu> <5460@june.cs.washington.edu>
Organization: Harvard-Smithsonian Ctr. for Astrophysics
Lines: 41

In article <5460@june.cs.washington.edu>, pardo@june.cs.washington.edu (David Keppel) writes:
> >>mcdonald@uxe.cso.uiuc.edu writes:
> >>>[ Core has destructive read ]
> >henry@utzoo.uucp (Henry Spencer) writes:
> >>[ So do DRAMs ]
> ward@cfa.harvard.EDU (Steve Ward) writes:
> >[ No they don't, they're just shift registers ]
> 

> Each capacitor is tied to the gate of a transistor, so that when you
> put current in the collector, current will come out the emitter if and
> only if the capacitor was charged.  In the actual construction of the
> DRAM, the capacitor is actually part of the transistor.
> 

> The only trick in this is that the capacitor, if it was charged
> initially, has since been discharged as it provided current for the
> transistor to conduct.  The on/off-ness of the particular row has
> moved out of the capacitors and in to the amplifiers.  The amplifiers
> (which are driving multiplexers and other amplifiers that drive the
> data lines) *also* drive the column wires.  Since the capacitor is
> actually part of the transistor, the voltage appearing on the column
> wire will recharge the capacitor.
> 
>     {rutgers,cornell,ucsd,ubc-cs,tektronix}!uw-beaver!june!pardo

Well folks, it looks like the DRAM memory cell content is essentially
destroyed by readout, though by design it looks like rewrite/refresh
is inherent in reading.  I guess the amplifiers have a sample/hold
or similar capability as the data can be held on the bus for a variable
period of time, which I speculate is well beyond the gate capacitor
discharge time.  The similarities are quite evident between the
old magnetic core sense/restore circuit and the above DRAM
description.

Now that I know all about DRAM's, will somebody give me some?  :-)

(only 256K and 1M denominations accepted!)

Steve Ward
ward@cfa