Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!ucsd!ucsdhub!hp-sdd!hplabs!hpda!hpcuhb!rb
From: rb@hpcuhb.HP.COM (Robert Brooks)
Newsgroups: comp.arch
Subject: Re: History of personal computing (LONG)
Message-ID: <3830002@hpcuhb.HP.COM>
Date: 10 Aug 88 17:43:56 GMT
References: <5946@venera.isi.edu>
Organization: Hewlett Packard, Cupertino
Lines: 21

> 
> A DRAM is made up of one or more circular, dynamic shift registers with
> read/write/address logic.  As the bits circulate through the shift
> registers, the data decays.  This is because the shift registers are
> analog and the data are electrical charges.  This means that
> periodically the charges must be reamplified.  The act of reading a
> DRAM will cause this reamplification, as will other methods (RAS-only
> access, for example).
> 
> Reading does not destroy the data.  The critical timing and special
> refresh considerations are related to the dynamic shift register
> nature of storage and access and the requirement to reamplify the
> shift register charges.

Where did you get this "shift register" business??  The storage mechanism
of a DRAM is a charge stored on the gate of a FET.  I believe a MOS
capacitor (in addition to the inherent gate capacitance) is necessary
to achieve the required capacitance, though this may not be the case
in all designs.  Reading would tend to be destructive of this charge
via coupling through the FET, so a hidden, internal "write" is performed.
Also, periodic refresh is needed due to leakage.