Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!ucsd!ucsdhub!hp-sdd!hplabs!hpda!hpcuhb!hpihoah!fotland From: fotland@hpihoah.HP.COM (Dave Fotland) Newsgroups: comp.arch Subject: Re: History of personal computing (LONG) Message-ID: <4420005@hpihoah.HP.COM> Date: 10 Aug 88 17:03:54 GMT References: <5946@venera.isi.edu> Organization: Hewlett Packard, Cupertino Lines: 31 / hpihoah:comp.arch / ward@cfa.harvard.EDU (Steve Ward) / 3:41 pm Aug 9, 1988 / In article <1988Aug8.163944.29383@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: >> >> Dynamic RAMs are the same way (destructive readout), although many >> people aren't aware >> of this because the chips hide most of the ugly details. >actually, this is not correct. >Dynamic RAM does not have destructive readout. In fact, the DRAM is >refreshed with a read-only cycle in typical applications. DRAM's do >have special timing and refresh considerations, though. >A DRAM is made up of one or more circular, dynamic shift registers with >read/write/address logic. As the bits circulate through the shift >registers, the data decays. This is because the shift registers are >analog and the data are electrical charges. This means that >periodically the charges must be reamplified. The act of reading a >DRAM will cause this reamplification, as will other methods (RAS-only >access, for example). >Reading does not destroy the data. The critical timing and special >refresh considerations are related to the dynamic shift register >nature of storage and access and the requirement to reamplify the >shift register charges. I can't believe he said this! DRAM's are not made out of shift registers! Internally, each bit is stored on a capacitor and it is lost during reading and is rewritten internal to the ram so you don't have to worry about it at the system level. There are zillions of papers and books on how DRAM's work if you are interested in more details.