Path: utzoo!dciem!dretor!client2!king From: king@client2.DRETOR.UUCP (Stephen King) Newsgroups: comp.sys.amiga Subject: Re: Clarify Perry's AC "PAL Help" article Message-ID: <765@client2.DRETOR.UUCP> Date: 12 Jul 88 13:11:50 GMT Article-I.D.: client2.765 References: <1666@vu-vlsi.Villanova.EDU> Reply-To: king@client2.UUCP (Stephen King) Distribution: na Organization: D.C.I.E.M., Toronto, Canada Lines: 31 In article <1666@vu-vlsi.Villanova.EDU> sword@vu-vlsi.Villanova.EDU (David Talmage) writes: >In _Amazing Computing_ Volume 3, Number 3, Perry Kivolowitz tells us how >to improve the grounding of four PALS on the daughter board of our A1000's. >This change may make the A1000 less prone to mysteriously crashing. I found this mod necessary when using a 2Meg board & Comspec SCSI adaptor slapped onto my 1000 here at work. >My problem: the text and the illustration don't agree. The text says to >connect the top left pins of PALs J&K and L&N. The picture shows J&K >connected per the text but L&N aren't connected by their top left pins. >Instead, the picture shows L&*K* connected by their top *right* pins. I don't have the illustration to look at, but here is what I did: Connect: J10-K10-L10-N10-P11-Q11-MotherBoardGround It seems that J,K,L & N should all have the same pins grounded, but P & Q use the pins on the other side of the package. This is because some chips are viewed from the bottom and others from the top. When in doubt, check the data sheet for the chip. Most (normal) chips have ground in the bottom left corner of the package, when viewed from the top with the little notch upwards (pin 1 in upper left corner). +5V supply is the top right pin, diagonally opposed to ground. Note that dynamic RAM chips are (always ?) backwards, presumeably because they were invented by IBM :-) * These are the facts as I understand them, my employer may or may not agree, depending on the prevailing wind and other important factors. --- Stephen J King - Simulation & Training, DCIEM - ...{utzoo|mnetor}!dciem!dretor!king (at least, for the time being)