Path: utzoo!attcan!uunet!tektronix!orca!tekecs!frip!andrew From: andrew@frip.gwd.tek.com (Andrew Klossner) Newsgroups: comp.arch Subject: Re: Gemini Message-ID: <10165@tekecs.TEK.COM> Date: 14 Jul 88 20:38:58 GMT References: <3300030@uiucdcsm> <6954@cup.portal.com> <28200171@urbsdc> Sender: andrew@tekecs.TEK.COM Organization: Tektronix, Wilsonville, Oregon Lines: 20 [] "As for RISC and the 432, I think it's something like this. Build a RISC machine with a load/store architecture, single-cycle instructions, lots of pipelining, a big register set, etc. Then add microcode support for complex data type and complex instructions, and also for concurrency support and task switching. You can stick to the RISC instructions and run as fast as a pure RISC machine, or use the complex instructions if they're useful to you." Hillsboro scuttlebutt has it that the 80960 has all the object-oriented and silicon operating system cruft of the 432, but if all you document are the RISCy instructions, you can call it a RISC. From a market viewpoint, if it does what it's documented to do, it does it fast, and it's cheap, it really doesn't matter what's inside. -=- Andrew Klossner (decvax!tektronix!tekecs!andrew) [UUCP] (andrew%tekecs.tek.com@relay.cs.net) [ARPA]