Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!uwvax!vanvleck!uwmcsd1!ig!agate!ucbvax!decwrl!decvax!tektronix!orca!tekecs!frip!andrew From: andrew@frip.gwd.tek.com (Andrew Klossner) Newsgroups: comp.arch Subject: Re: M88000 power dissipation as a function of programming Message-ID: <10157@tekecs.TEK.COM> Date: 12 Jul 88 04:48:07 GMT References: <1370@claude.oakhill.UUCP> Sender: andrew@tekecs.TEK.COM Organization: Tektronix, Wilsonville, Oregon Lines: 26 A few nits ... > r2: 0x55555555 > r3: 0xAAAAAAAA > 0xFFFFFFFC: > st r2,r3,r0 > br.n -1 > st r3,r2,r0 Under normal circumstances, each store will cause a misaligned data access exception because the target addresses are not longword-aligned. You can disable this exception by manipulating a bit in the PSR, but I've never been able to figure out just what happens in that case, except that a 68020-style unaligned longword store (straddling two adjacent aligned longwords) doesn't. > I-Address D-Address Data Byte Strobe > (30 bits) (30 bits) (32 bits) (4 bits) > -------- -------- -------- - > 3FFFFFFF 55555555 AAAAAAAA F You can't get 55555555 in 30 bits. The D-address will be 15555555. Will the byte strobe really be F for this misaligned access? -=- Andrew Klossner (decvax!tektronix!tekecs!andrew) [UUCP] (andrew%tekecs.tek.com@relay.cs.net) [ARPA]