Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!cornell!batcomputer!itsgw!steinmetz!davidsen From: davidsen@steinmetz.ge.com (William E. Davidsen Jr) Newsgroups: comp.sys.ibm.pc Subject: Re: GATHER and say NO to MCA! Message-ID: <11463@steinmetz.ge.com> Date: 5 Jul 88 18:39:18 GMT References: <42900016@uicsrd.csrd.uiuc.edu> <257@octopus.UUCP> <23590@bu-cs.BU.EDU> Reply-To: davidsen@crdos1.UUCP (bill davidsen) Organization: General Electric CRD, Schenectady, NY Lines: 17 There is a bus which allows multiple masters (DMA and CPUs look the same) with a priority scheme, stacked interrupts, etc. It even allows diferrent CPUs to reprioritize the interrupt handling. It has been in continuous production since 1976 and is available with all Intel processors (I suspect the 432 is no longer sold), 68k and NS32k family, etc. This is the IEEE696 standard bus. The last time I looked there were about 80 vendors selling hardware for it. It's a true backplane system, no motherboard functions, and you can switch or add processors at will, or run wierd things like a 68010 and 386 on the same system (yes I use custom software). It supports UNIX and MSDOS implementations on appropriate CPU's. -- bill davidsen (wedu@ge-crd.arpa) {uunet | philabs | seismo}!steinmetz!crdos1!davidsen "Stupidity, like virtue, is its own reward" -me