Path: utzoo!utgpu!water!watmath!clyde!att!ucbvax!decwrl!nsc!taux01!yuval
From: yuval@taux01.UUCP (Gideon Yuval)
Newsgroups: comp.arch
Subject: Re: m88000 benchmarks (LONG)
Keywords: m88000 benchmark fft instruction scheduling
Message-ID: <830@taux01.UUCP>
Date: 13 Jul 88 12:38:53 GMT
References: <1359@claude.oakhill.UUCP>
Reply-To: yuval@taux01.UUCP (Gideon Yuval)
Organization: National Semiconductor (Israel) Ltd.
Lines: 13

In his 6/88 posting, William Anderson of Motorola says:
> The code from compiler A for the inner loop is 39 instructions and, as
> scheduled by compiler A, requires 75 clocks to execute.  Although
> compiler A is supposed to have a Motorola-developed instruction
> scheduling strategy incorporated in it, we can filter the above code
> through the Motorola instruction scheduler to get a code sequence which
> executes in 64 clocks.  Both code sequences are given below:

Is this instruction-scheduler available to the public?
-- 
Gideon Yuval, yuval@taux01.nsc.com, +972-2-690992 (home) ,-52-522255(work)
 Paper-mail: National Semiconductor, 6 Maskit St., Herzliyah, Israel
             (alternative E-mail address: decwrl!nsc!taux01!yuval@uunet.uu.net)