Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!iuvax!pur-ee!a.cs.uiuc.edu!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: 88k trick for FP abs/neg
Message-ID: <28200174@urbsdc>
Date: 7 Jul 88 15:15:00 GMT
References: <2553@obiwan.mips.COM>
Lines: 40
Nf-ID: #R:obiwan.mips.COM:2553:urbsdc:28200174:000:1859
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jul  7 10:15:00 1988


>In article <10136@tekecs.TEK.COM>, andrew@frip.gwd.tek.com (Andrew Klossner)
>writes
>	> To clear up a question: on the 88k, floating point values are
>	> kept in general registers, so "abs" is done by ANDing to 0 the
>	> sign bit, "neg" is done by XORing the sign bit, and "mov" is
>	> done with conventional register-to-register move instructions.
>
>Oughtn't the operand be first tested for "IEEE-ness"?  Specifically,
>what if the operand of  neg  is a Signaling NaN?  Oughtn't this cause
>an invalid operation exception?
>
>Or perhaps this a case of "should" versus "shall" in the IEEE spec.....
>
> -- Mark Johnson	
> 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086

My copy says "Signaling NaNs shall be reserved operands that signal
the invalid operation exception for every operation listed in
Section 5. Whether copying a signaling NaN without a change of format
signals the invalid operation exception is the implementor's option".
	"neg" doesn't seem to be explicitly called out, but is
implied by subtraction, I think, as one of the operations.
	Of course, signalling NaNs must be able to set a flag
when encountered, but need not (should) trap.

The question is, of course, whether an explicit test for NaNness
followed by conventional arithmetic might not be faster than
a special purpose FP instruction that combines the test and the
NaN detection flag setting.


Andy "Krazy" Glew. Gould CSD-Urbana.    1101 E. University, Urbana, IL 61801   
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