Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!uwvax!vanvleck!uwmcsd1!ig!agate!ucbvax!decwrl!decvax!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.gwd.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: Re: RISC machines and scoreboarding
Message-ID: <10158@tekecs.TEK.COM>
Date: 12 Jul 88 05:04:02 GMT
References: <1362@oakhill.UUCP> <2547@wright.mips.COM>
Sender: andrew@tekecs.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 15

Earl Killian wrote:

	"When you build a R3000-based MP, you don't have to limit the
	amount of cache per processor (unlike, e.g., the 88000, which
	allows only 16KB per processor in a 4-processor system)."

Presumably Earl meant "data cache" where he wrote "cache."
Just to keep the record straight: in a 4-processor 88k system on a
single M-bus (the bus implemented by the CMMU pinouts), each processor
has 16KB data cache and 16KB instruction cache, for a total of 32KB
cache.  If you want more than that, you need more than one M-bus.  Some
system designers are doing this.

  -=- Andrew Klossner   (decvax!tektronix!tekecs!andrew)       [UUCP]
                        (andrew%tekecs.tek.com@relay.cs.net)   [ARPA]