Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!mit-eddie!killer!pollux!ti-csl!pf@csc.ti.com From: pf@csc.ti.com (Paul Fuqua) Newsgroups: comp.arch Subject: Re: getting rid of branches Message-ID: <53161@ti-csl.CSNET> Date: 4 Jul 88 05:13:20 GMT References: <28200173@urbsdc> Sender: news@ti-csl.CSNET Organization: TI Computer Science Center, Dallas Lines: 36 Date: Friday, July 1, 1988 8:59am (CDT) From: aglew at urbsdc.Urbana.Gould.COM This comes perilosly close to something I'm trying. Davidson at the UIll, now UMich, proposed a partitioned access/execute architecture a while back, where you basically have two processors, one for address and memory computations, one for (mainly floating point?) calculation. They run independently, with FIFOs between them for passage of variables back and forth, condition codes, etc. They basically run two versions of exactly the same program, one with all the FP taken out, and the other with all the memory references replaced by "get the next value from the memory unit". Anyone else doing similar? I have a copy of a paper, "PIPE: A VLSI Decoupled Architecture," by James R Goodman and five others, that appeared in a 1985 IEEE something (sorry, it's not noted on my copy). PIPE uses two processors connected by queues: "Each of PIPE's processors is capable of executing an entire program by itself (in SP -- single processor -- mode), or the two processors may work together on a program (in AE -- access/execute -- mode)." In detail, it's quite similar to the description above, with the addition of more queues in the memory system (that don't connect the processors), and a strange sort of variable-delay branch. The work was done at the University of Wisconsin-Madison. Is anyone outside the Great Lakes states working on this idea? pf Paul Fuqua Texas Instruments Computer Science Center, Dallas, Texas CSNet: pf@csc.ti.com (ARPA too, sometimes) UUCP: {smu, texsun, cs.utexas.edu, im4u, rice}!ti-csl!pf