Path: utzoo!attcan!uunet!husc6!mailrus!iuvax!pur-ee!hankd From: hankd@pur-ee.UUCP (Hank Dietz) Newsgroups: comp.arch Subject: Re: Superoptimiser. Summary: Output-enabling and Cydra Message-ID: <8446@pur-ee.UUCP> Date: 5 Jul 88 17:26:21 GMT References: <834@garth.UUCP> <4014@korppi.tut.fi> Organization: Purdue University Engineering Computer Network Lines: 17 In article <4014@korppi.tut.fi>, pl@tut.fi (Pertti Lehtinen) writes: > When avoiding branches, interesting technique is adopted in > ARM-processor (Acorn Risc Machine). All instructions are > conditional, which makes it possible to avoid short branches > very easily. A similar technique is used in the Cydra machine... as I understand it, this machine performs VLIW-like scheduling of blocks of code (relatively conventional control-flow stuff) and simply enables/disables output arcs (i.e., stores) based on condition inputs for each block. In other words, you can execute both sides of a branch intermingled, then decide to ignore the results of either. I hav e only a single literature sheet on this architecture, however. Anyone have more details? -hankd