Xref: utzoo comp.lang.c:11334 comp.arch:5501 Path: utzoo!utgpu!water!watmath!clyde!att!ucbvax!hplabs!amdcad!tim From: tim@amdcad.AMD.COM (Tim Olson) Newsgroups: comp.lang.c,comp.arch Subject: Re: Self-modifying code Message-ID: <22375@amdcad.AMD.COM> Date: 15 Jul 88 17:50:53 GMT References: <3353@cognos.UUCP> <619@goofy.megatest.UUCP> <429@uwovax.uwo.ca> <33518@yale-celray.yale.UUCP> <1087@ficc.UUCP> Reply-To: tim@delirun.amd.com (Tim Olson) Organization: Advanced Micro Devices Lines: 13 Summary: Expires: Sender: Followup-To: In article <1087@ficc.UUCP> peter@ficc.UUCP (Peter da Silva) writes: | I have a question: | | Why are an Icache plus a Dcache better than just | a big shared cache as big as both? When the processor has separate instruction and data buses, so concurrent accesses can occur to both caches. -- -- Tim Olson Advanced Micro Devices (tim@delirun.amd.com)