Path: utzoo!attcan!uunet!husc6!mailrus!cornell!uw-beaver!uw-june!pardo
From: pardo@june.cs.washington.edu (David Keppel)
Newsgroups: comp.arch
Subject: Re: Memory latency / cacheing / scientific programs
Message-ID: <5230@june.cs.washington.edu>
Date: 5 Jul 88 21:09:50 GMT
References: <243@granite.dec.com> <779@garth.UUCP> <2033@pt.cs.cmu.edu> <11106@ames.arc.nasa.gov> <8444@pur-ee.UUCP>
Reply-To: pardo@uw-june.UUCP (David Keppel)
Organization: U of Washington, Computer Science, Seattle
Lines: 9

In article <8444@pur-ee.UUCP> hankd@pur-ee.UUCP (Hank Dietz) writes:
[ You may need more... but 16 registers seems to be enough ]

See papers by David Wall (1986 ACM??, ??) on global register
allocation at link time.  (Talk about global optimization!).
He's had very good results with a machine using about (read
"more than") 50 registers.

	;-D on  ( ZERO tolerance on drugs: impeach Bush )  Pardo