Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!ubvax!vsi1!wyse!mips!earl
From: earl@mips.COM (Earl Killian)
Newsgroups: comp.arch
Subject: Re: RISC machines and scoreboarding
Message-ID: <2548@wright.mips.COM>
Date: 6 Jul 88 03:48:56 GMT
References: <1362@oakhill.UUCP>
Lines: 55
In-reply-to: mpaton@oakhill.UUCP's message of 1 Jul 88 20:57:15 GMT

In article <1362@oakhill.UUCP> mpaton@oakhill.UUCP (Michael Paton) writes:

mp> Independent of this current discussion on the length of load
mp> pipelines, one might want to ask the folks at MIPS Co. this
mp> question:
mp>            Why did you multiplex your memory bus?
mp> Consider factors related to power dissipation.  The current M88100
mp> processors are running between .25 and .5 watts @ 20Mhz.  If we
mp> were to multiplex the 2 memory ports as did MIPS Co., our worst
mp> case power consumption would be 4 watts.  The problem is that the
mp> AC power dissipation is given by:
mp>                          2*C*V**2*F*N,          
mp>                 N = number of pins which make transitions.
mp> The addresses from the instruction port are very highly correlated
mp> (about 1.4 bits per cycle change).  The addresses from the data
mp> port are only partially correlated (less so with better
mp> compilers).  Mixing these two streams results in almost
mp> uncorrelated address streams and therefore a bigger N, resulting
mp> in more power dissipation.

Your observation is interesting.  But I hope the 88100's packaging
isn't based on an _average_case_ analysis.  Malicious programmers (who
write, for example, a branch-to-branch infinite loop) can't melt the
88100, can they?  So the worse case is really 4 watts, right?  What
does the datasheet say?

Also the cpu subsystem power consumption isn't much reduced by your
observation, since it only applies to the address outputs on the cpu,
which is a small fraction of the total pins in the system (the I-cache
SRAM pins change every cycle even if the address doesn't change much).
Hmm, I guess the address outputs in an 88000 system are a significant
fraction of the pins, unlike the R3000, because you send the full 32b
virtual address off chip, instead of only 18b as in the R3000.  That
wastes as much power as you save on average from the demultiplexing,
doesn't it?


mp> Notice that the pin counts on the two packages are not that much
mp> different (144 for the R3000 vs. 180 for the MC88100) and neither
mp> are the power/grounds pin counts (30 for the R3000 vs. 36 for the
mp> MC88100).

MIPS designed its first RISC chip (the R2000) 4 years ago, and at that
time the difference between 180 pins and 144 pins was significant.
The i80386, designed at roughly the same time, actually has fewer
pins -- 132.  The 2nd generation (R3000) could have changed the
interface, but we felt it was desirable to provide an upgrade path for
R2000 designs.

Back when RISC vs. CISC was still an issue, people complained RISC
required more bandwidth.  We just provided the necessary bandwidth.
When we need more, we'll add more.  If that means modifying the
R3000-style cache interface, so what?
-- 
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