Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!amdcad!ames!ll-xn!mit-eddie!uw-beaver!tektronix!tekcrl!tekfdi!videovax!stever
From: stever@videovax.Tek.COM (Steven E. Rice, P.E.)
Newsgroups: comp.sys.amiga
Subject: Re: Another 68020 difference
Message-ID: <5075@videovax.Tek.COM>
Date: 29 Jun 88 19:23:36 GMT
References: <8806240024.AA11802@cory.Berkeley.EDU>
Reply-To: stever@videovax.Tek.COM (Steven E. Rice, P.E.)
Organization: Tektronix Television Systems, Beaverton, Oregon
Lines: 30

In article <8806240024.AA11802@cory.Berkeley.EDU>, Matt Dillon
(dillon@CORY.BERKELEY.EDU) writes:

> 	A friend of mine got caught by this one:
> 
> 	BSET is atomic, right?  OR.w #1,memory?
> 
> 	wrong
> 
> 	Guess what?  The 68020 has no compunction for interrupting an
> 	instruction in the middle of its execution.
> 
> 	So all those supposedly atomic single-instruction operations people
> have probably been doing, and not surrounding them with Forbid()/Permit(),
> create windows of vulnerability if you've got a 68020.

There is nothing in the chip that can prevent DMA hardware from getting in
between the read of the memory location and the write back to that location,
changing the contents of memory (which then gets clobbered by the results
of the instruction).  There is a line out of the processor (RMC*) which
indicates that memory should not be altered during TAS (test and set) and
CAS and CAS2 (compare and swap) instructions.  Note that the memory system
must be able to respond to this line, though!

					Steve Rice

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