Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!cornell!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!lindsay From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay) Newsgroups: comp.arch Subject: Re: Memory latency / cacheing / scientific programs Message-ID: <2033@pt.cs.cmu.edu> Date: 24 Jun 88 02:24:10 GMT References: <243@granite.dec.com> <779@garth.UUCP> Sender: netnews@pt.cs.cmu.edu Organization: Carnegie-Mellon University, CS/RI Lines: 20 In article <779@garth.UUCP> smryan@garth.UUCP (Steven Ryan) writes: >The scalar CPU of Cyber 205 can issue up to 3 loads/stores to the memory unit. >It continues running until the loaded register is referenced. According to "Lockup-Free Instruction Fetch/Prefetch Cache Organization" by David Kroft SIGARCH Vol 9 #3 p.81 (May 1981) (8th Annual Symposium on Computer Architecture) Control Data prototyped a cache which could continue satisfying cache hits at full pipeline speed, plus keep track of N unsatisfied cache misses. The article reported that N=4 seemed optimal in their case. (Kroft did not, however, say what machine the prototype was for.) -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science "Imitation is not the sincerest form of flattery. Payments are." - a British artist who died penniless before copyright law.