Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!husc6!purdue!decwrl!nsc!stevew From: stevew@nsc.nsc.com (Steve Wilson) Newsgroups: comp.arch Subject: Re: pad grid package Keywords: 88000, pad grid Message-ID: <5186@nsc.nsc.com> Date: 22 Jun 88 16:07:01 GMT References: <2016@pt.cs.cmu.edu> Reply-To: stevew@nsc.UUCP (Steve Wilson) Organization: National Semiconductor, Sunnyvale Lines: 21 In article <2016@pt.cs.cmu.edu> lindsay@k.gp.cs.cmu.edu (Donald Lindsay) writes: > >There hasn't been any discussion of the new package that Motorola announced >for its "Hypermodule". > >Basically, they are moving from pin-grid packages with 100-mil centers, to >pad-grids with 60-mil centers. This cleans up the board layout, since >buried layers don't have to make room for all those big fat pins. It also >increases the connections per square inch from 100 to 277, i.e. almost >triple the density. Specifically, it allows the 88100 CPU to have four >32-bit paths and still be in a package 1.1" on a side. > I just wonder how many board layout packages are broken by this new packaging scheme? I know alot of them are hard-wired to only be capable of working on 100 mil or 50 mil grid! Steve Wilson National Semiconductor [This is my opinion only, not that of my employer's]