Path: utzoo!attcan!uunet!husc6!cmcl2!nrl-cmf!ames!amdahl!pyramid!prls!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: The VAX Always Uses Fewer Instructions Keywords: VAX MIPS Message-ID: <2461@winchester.mips.COM> Date: 25 Jun 88 20:43:10 GMT References: <6921@cit-vax.Caltech.Edu> <28200161@urbsdc> <10595@sol.ARPA> <1277@basser.oz> <270@laic.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 23 In article <270@laic.UUCP> darin@nova.laic.uucp (Darin Johnson) writes: .... >The biggest drawback I can see, is that there would have to be 'optimizing >assemblers'. Of course, such an assembler would find it difficult to >take advantage of some common RISC idioms, such as register windows. Optimizing assemblers have existed for years, in various forms, and in many companies, on both CISC and RISC machines. Many RISC machines have optimizing assemblers, including such things as code scheduling, addressing-style optimization, optimization of constant creation, code selection for mulitply/divide by constants, etc, etc. We had the first version of the MIPSco one working BEFORE the R2000 architecture was even frozen, for example. At this point, optimization is moving further afield, i.e., one is even starting to see optimizing linkers [we do some of this, and I think Moto does also.] -- -john mashey DISCLAIMER:UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086