Path: utzoo!utgpu!water!watmath!clyde!mcdchg!nud!rover!mph From: mph@rover.UUCP (Mark Huth) Newsgroups: comp.sys.amiga Subject: Re: Another 68020 difference Message-ID: <783@rover.UUCP> Date: 24 Jun 88 23:49:47 GMT References: <8806240024.AA11802@cory.Berkeley.EDU> Reply-To: mph@rover.UUCP (Mark Huth) Organization: Motorola Microcomputer Division, Tempe, Az. Lines: 34 In article <8806240024.AA11802@cory.Berkeley.EDU> dillon@CORY.BERKELEY.EDU (Matt Dillon) writes: > > A friend of mine got caught by this one: > > BSET is atomic, right? OR.w #1,memory? > > wrong > > Guess what? The 68020 has no compunction for interrupting an > instruction in the middle of its execution. > > So all those supposedly atomic single-instruction operations people >have probably been doing, and not surrounding them with Forbid()/Permit(), >create windows of vulnerability if you've got a 68020. Well, I'm not sure what you mean by interrupting an instruction. The 68020 manual, on page 5-27 (1984 ed.) states that the exception processing for an interrupt begins at the next instruction boundary! There are cases where the 68020 will relinquish the bus without completing the data transfers for an instruction. There are no promises made that a read/modify/write instruction is indivisible except for TAS, CAS, and CAS2. If you need to synchronize multi-processors use the correct instructions. Certain exceptions will be taken in the middle of an instruction, but cause no problems as execution will resume (if possible) in the middle of the instruction once the exception is handled. If you have analyzer traces that demonstrate that an interrupt context change occurs in the middle of an instruction, we would like to see them at Motorola. Mark Huth