Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!husc6!uwvax!dogie!uwmcsd1!ig!agate!ucbvax!decwrl!pyramid!oliveb!intelca!mipos3!blabla!kds
From: kds@blabla.intel.com (Ken Shoemaker)
Newsgroups: comp.arch
Subject: Re: RISC machines and scoreboarding
Message-ID: <2417@mipos3.intel.com>
Date: 21 Jun 88 01:03:55 GMT
References: <1082@nud.UUCP> <2438@winchester.mips.COM>
Sender: nobody@mipos3.intel.com
Reply-To: kds@mipos2.intel.com. (Ken Shoemaker)
Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA
Lines: 23

But one very important constraint that John imposed was that the processor/
data memory system allow only one external data access at a time.  This
just isn't a requirement with the current level of integration possible on
chips: having multiple pending external cycles is something that is
certainly possible.  I don't know if the 88000 supports this, but judging
from some of the microarchitectural tradeoffs that they performed, it would
seem that they had something along these lines in mind, maybe in a future
chip?

Another thing that register scoreboarding can be used for is to prefetch
data into caches: if you know that you are going to use a particular vector
at some time in the future, you can preload it into the cache so that it
is available when you get back to it.  This certainly is a more elegant
solution than a "do the load, but don't wait for the data to ever come back"
method of doing the same thing.  This could be useful when working with
very large data sets, i.e., those that don't fit into your cache in a
typical system where the main memory latency is long, but transfer time is
short.  But what do I know?  And why am I defending Mot?

You don't have to break many eggs to hate omlets -- Ian Shoales

Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
uucp: ...{hplabs|decwrl|amdcad|qantel|pur-ee|scgvaxd|oliveb}!intelca!mipos3!kds