Path: utzoo!attcan!uunet!tektronix!orca!tekecs!frip!andrew From: andrew@frip.gwd.tek.com (Andrew Klossner) Newsgroups: comp.arch Subject: Re: m88k memory stalls (was: RISC machines and scoreboarding) Message-ID: <10122@tekecs.TEK.COM> Date: 28 Jun 88 16:04:15 GMT References: <1082@nud.UUCP> <2438@winchester.mips.COM> <1098@nud.UUCP> <2465@winchester.mips.COM> <28981@pyramid.pyramid.com> Sender: andrew@tekecs.TEK.COM Organization: Tektronix, Wilsonville, Oregon Lines: 24 |>> For example, in the following code sequence |>>(assume the ld is a cache miss): | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |>> |>>1) ld r2,r3,0 ; Get value. |>>2) add r3,r3,16 ; Bump pointer |>>3) add r2,r2,1 ; Increment value. |>>4) sub r4,r4,1 ; Dec count. |>> |>>the instruction unit will stall on instruction 3 since it attempts to |>>use stale data. | |>Thanx: we weren't sure whether it had multiple streams or not. |>The example seems to indicate that the 88K indeed has a load with |>2 cycles of latency (i.e., cycles 2 & 3 above). | |Tom said to assume that the load caused a cache miss, so the example |given does not imply that the load has 2 delay cycles. On the 88k, a load on cache hit does in fact have two delay cycles. The data memory load/store pipeline is three deep. -=- Andrew Klossner (decvax!tektronix!tekecs!andrew) [UUCP] (andrew%tekecs.tek.com@relay.cs.net) [ARPA]