Path: utzoo!attcan!uunet!husc6!mailrus!ames!hc!lanl!beta!jlg
From: jlg@beta.lanl.gov (Jim Giles)
Newsgroups: comp.arch
Subject: Re: The VAX Always Uses Fewer Instructions
Keywords: VAX MIPS
Message-ID: <20424@beta.lanl.gov>
Date: 24 Jun 88 15:53:49 GMT
References: <6921@cit-vax.Caltech.Edu> <28200161@urbsdc> <10595@sol.ARPA> <270@laic.UUCP>
Organization: Los Alamos National Laboratory
Lines: 22

In article <270@laic.UUCP>, darin@nova.laic.uucp (Darin Johnson) writes:
> [...]
> Perhaps it would be possible for someone to come up with an 'assembler-compiler'
> that would accept a CISC instruction set and generate RISC code.  This would
> allow one to write using something like 'ADD mem-loc1 to mem-loc2 and store
> to mem-loc3(R1)' without having  write the 5 or 10 RISC lines of code.
> The biggest drawback I can see, is that there would have to be 'optimizing
> assemblers'.  Of course, such an assembler would find it difficult to 
> take advantage of some common RISC idioms, such as register windows.

This is already possible with macros, opdefs, and micros that many
assemblers have.  Just define one of these for each CISC instruction
mnemonic you wish to emulate.  (OK. The syntax for defining these may
be messy, but it could be made to work.)

As you pointed out, there is a need for optimizing assemblers.  This
need already exists for macro assemblers since hand pipelining a code
is not possible through macro calls.  The Cray has needed such an
optimizing assembler for years.

J.Giles
Los Alamos