Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!lamaster From: lamaster@ames.arc.nasa.gov (Hugh LaMaster) Newsgroups: comp.arch Subject: Re: Memory latency / cacheing / scientific programs Message-ID: <11023@ames.arc.nasa.gov> Date: 29 Jun 88 16:18:11 GMT References: <243@granite.dec.com> <779@garth.UUCP> <2033@pt.cs.cmu.edu> <803@garth.UUCP> Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) Organization: NASA Ames Research Center, Moffett Field, Calif. Lines: 18 In article <803@garth.UUCP> smryan@garth.UUCP (Steven Ryan) writes: >Actually, I don't know if a 205 even has a cache. If it does, it is well >hidden from the CPU. I think the main memory is supposed to be as fast as >cache memory on all these weeny machine (ha-ha). Neither the 205 nor the Cray has a cache. The philosophy is to put in enough registers that a cache is unnecessary. The 256 registers on the 205 were plenty for any module that I saw. The place where this approach hurts is in scalar codes that have very frequent procedure calls (typical C system and utilities code) since data has to be saved and restored between procedure calls even if it is being reused. So, don't run code like that on these machines more than necessary... -- Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117