Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!cornell!batcomputer!itsgw!nyser!njin!aramis.rutgers.edu!porthos.rutgers.edu!webber From: webber@porthos.rutgers.edu (Bob Webber) Newsgroups: comp.arch Subject: Optimizing Assemblers (was: Re: The VAX Always Uses ...) Keywords: VAX MIPS Message-ID:Date: 24 Jun 88 01:34:46 GMT References: <6921@cit-vax.Caltech.Edu> <28200161@urbsdc> <10595@sol.ARPA> <270@laic.UUCP> Organization: Rutgers Univ., New Brunswick, N.J. Lines: 12 In article <270@laic.UUCP>, darin@nova.laic.uucp (Darin Johnson) writes: >... > The biggest drawback I can see, is that there would have to be 'optimizing > assemblers'. Of course, such an assembler would find it difficult to > take advantage of some common RISC idioms, such as register windows. Actually there is a -O optimize option on all the Sun assemblers (for span dependent jumps and such), but with the Sun 4 (SPARC chip) it now takes a numeric option for level of peephole optimization (apparently meant to be backend for compiler-generated assembler). ----- BOB (webber@athos.rutgers.edu ; rutgers!athos.rutgers.edu!webber)