Path: utzoo!attcan!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com Newsgroups: comp.arch Subject: Re: Gemini Message-ID: <6954@cup.portal.com> Date: 29 Jun 88 04:02:02 GMT References: <3300030@uiucdcsm> Organization: The Portal System (TM) Lines: 24 XPortal-User-Id: 1.1001.4222 >So, Electronic News and some other rag had articles on the P7 (aka gemini) >project at Intel, and the formation of BiiN (right name?), a jointly >owned Siemans and Intel company. > >Any news about this? Speculations? My guess is that BiiN is going to use an implementation of the 80960 archi- tecture, whose initial implementation is now being sold as an embedded control processor. I suspect the BiiN version will have multiple instruction pipelines and other goodies to greatly increase performance over the existing 7.5 MIPS chips. As for RISC and the 432, I think it's something like this. Build a RISC machine with a load/store architecture, single-cycle instructions, lots of pipelining, a big register set, etc. Then add microcode support for complex data type and complex instructions, and also for concurrency support and task switching. You can stick to the RISC instructions and run as fast as a pure RISC machine, or use the complex instructions if they're useful to you. Now the RISC purists I'm sure would argue that all this complex stuff can't help but slow down the basic instruction set. But it might be worth it. Michael Slater, Editor and Publisher, Microprocessor Report mslater@cup.portal.com sun!portal!cup.portal.com!mslater 415/494-2677