Path: utzoo!utgpu!water!watmath!clyde!att!mtunx!pacbell!ames!ncar!noao!nud!tom From: tom@nud.UUCP (Tom Armistead) Newsgroups: comp.arch Subject: Re: RISC machines and scoreboarding Message-ID: <1097@nud.UUCP> Date: 22 Jun 88 16:43:24 GMT References: <1082@nud.UUCP> <2438@winchester.mips.COM> <2417@mipos3.intel.com> Reply-To: tom@nud.UUCP (Tom Armistead) Organization: Motorola Microcomputer Division, Tempe, Az. Lines: 39 In article <2417@mipos3.intel.com> kds@mipos2.intel.com. (Ken Shoemaker) writes: >But one very important constraint that John imposed was that the processor/ >data memory system allow only one external data access at a time. This >just isn't a requirement with the current level of integration possible on >chips: having multiple pending external cycles is something that is >certainly possible. I don't know if the 88000 supports this, but judging It does, up to 3 memory transactions (4 in a special case) can be pending simultaneously. 2 of the transactions can be in progress at the same time (although at different stages of completion) on the external bus (the PBUS). For example, the following sequence can be done ld r1,r2,0 st r3,r4,0 ld r5,r6,0 and all 3 transactions will be then be simultaneously in progress by the memory unit. The PBUS timing would look like (assuming cache hits): Clock PBUS address PBUS data PBUS R/W PBUS response 1 rise r2 - R - 1 fall r2 - R - 2 rise r4 data at *r2 W - 2 fall r4 data in r3 W SUCCESS to ld 3 rise r6 data in r3 R - 3 fall r6 - R SUCCESS to st 4 rise - data at *r6 - - 4 fall - - - SUCCESS to ld Briefly put, the address lines on the current clock tick correspond to the next ticks data lines and the current tick data lines corresponds to the previous tick address lines so 2 transactions are in progress at the same time. This allows a memory access to be completed each clock tick on a sustained basis. -- Just a few more bits in the stream. The Sneek