Path: utzoo!attcan!uunet!husc6!mailrus!iuvax!pur-ee!uiucdcs!uxc.cso.uiuc.edu!urbsdc!aglew From: aglew@urbsdc.Urbana.Gould.COM Newsgroups: comp.arch Subject: Re: RISC machines and scoreboarding Message-ID: <28200166@urbsdc> Date: 20 Jun 88 16:13:00 GMT References: <1082@nud.UUCP> Lines: 14 Nf-ID: #R:nud.UUCP:1082:urbsdc:28200166:000:704 Nf-From: urbsdc.Urbana.Gould.COM!aglew Jun 20 11:13:00 1988 > On RISC processors without a scoreboard*, how are the results of memory >references guaranteed to be available before they are used in subsequent >computations? I thought through several scenarios and couldn't find a very >good solution and being being unfamiliar with RISCs other than the 88k, >thought the net might have some answers. >... >2) If the compiler/assembly writer is required to wait a certain number >of ticks after a load before using the results of the load, how is the >required amount of delay determined? Can you assume you always get a >cache hit (I doubt it)? Usually by assuming a cache hit; the entire processor stalls on a cache miss. Details of the stall may vary.