Path: utzoo!attcan!uunet!husc6!bbn!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!lindsay
From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: pad grid package
Keywords: 88000, pad grid
Message-ID: <2016@pt.cs.cmu.edu>
Date: 21 Jun 88 15:35:40 GMT
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 35


There hasn't been any discussion of the new package that Motorola announced
for its "Hypermodule".

Basically, they are moving from pin-grid packages with 100-mil centers, to
pad-grids with 60-mil centers.  This cleans up the board layout, since
buried layers don't have to make room for all those big fat pins.  It also
increases the connections per square inch from 100 to 277, i.e.  almost
triple the density.  Specifically, it allows the 88100 CPU to have four
32-bit paths and still be in a package 1.1" on a side.

This is Neat, of course, because density equates to progress. (I remember
the backpanel of the PDP-5: it looked like you soldered the pins with a 50
watt iron. I tried to look inside an LGP-30 (drum machine) once, but the
wire mat was too many inches thick to see through.)

I have a few questions. For one, why did Motorola feel the need to use 102
pads (YES - ONE HUNDRED AND TWO PADS) just to conduct heat? (And what do
TAB packagers do with heat?)

I suppose that this package will allow higher clock rates than pin grid
arrays do. Do we have any experts on the net, who can comment on how soon
that will actually matter?

Also, it used to be that package designers were very worried about allowing
visual inspection of joints (IBM notwithstanding). Did this worry just go
away? Can these things be socketed?



-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science

"Imitation is not the sincerest form of flattery. Payments are."
- a British artist who died penniless before copyright law.