Path: utzoo!utgpu!water!watmath!clyde!bellcore!faline!thumper!ulysses!andante!amdcad!rpw3 From: rpw3@amdcad.UUCP Newsgroups: comp.lang.c Subject: Re: volatile (in comp.lang.c) Message-ID: <21973@amdcad.AMD.COM> Date: 5 Jun 88 06:52:47 GMT References: <20345@pyramid.pyramid.com> <833@mcdsun.UUCP> <1988May23.003847.1114@utzoo.uucp> <21821@amdcad.AMD.COM> <1036@ima.ISC.COM> Reply-To: rpw3@amdcad.UUCP (Rob Warnock) Organization: [Consultant] San Mateo, CA Lines: 29 In article <1036@ima.ISC.COM> johnl@ima.UUCP (John R. Levine) writes: +--------------- | In article <21821@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes: | >The "volatile" type is necessary and sufficient for correctly implementing | >Dekker's Algorithm in "optimizing C". | Not so fast, there. In large multi-CPU systems, there is often a write-behind | cache and writes by one processor are not always visible to other processors | until you do some sort of cache-flush operation... +--------------- I'm sorry, I was talking about the programming language considerations. Of course you are correct about the larger systems issue. I was assuming that any data pages used for inter-processor sychronization would be flagged as "don't cache" to the MMU/cache. (Most MMU's have some way to indicate to the cache that given pages are not to be cached, but that reads/writes are to be made directly to memory.) Even if you have special semaphore hardware ("magic" memory locations), you still must flag them as "don't cache"... Rob Warnock Systems Architecture Consultant UUCP: {amdcad,fortune,sun,attmail}!redwood!rpw3 ATTmail: !rpw3 DDD: (415)572-2607 USPS: 627 26th Ave, San Mateo, CA 94403