Path: utzoo!attcan2!uunet!husc6!cmcl2!nrl-cmf!ames!joyce!sri-unix!garth!walter
From: walter@garth.UUCP (Walter Bays)
Newsgroups: comp.arch
Subject: Re: 88k register sets?
Message-ID: <684@garth.UUCP>
Date: 1 Jun 88 15:40:36 GMT
References: <631@necis.UUCP>
Reply-To: walter@garth.UUCP (Walter Bays)
Distribution: na
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 34
Posted: Wed Jun  1 08:40:36 1988

In article <631@necis.UUCP> smv@necis.UUCP (Steve Valentine) writes:
>In the 4/28/88 issue of Electronics on pg. 86, 2nd column there is a paragraph
>which reads as follows:
>
>"Features of the 88000 that suit it to use as a server include its register-
>scoreboarding capability, which makes it possible to for the system to switch
>from one task to another (called a context switch) in one clock cycle.  To do
>this, the 88100 chip has duplicate sets of CPU registers used by different tasks
>running concurrently in the system.  Switching from one task to another requires
>only a change in register sets." 
>
>This is the only mention I have seen of the 88k having multiple register sets.
>Is this really true?

According to the technical summary (document BR588/D; you can get one
by calling Motorola) the 88100 has 32 general purpose registers, 1
wired to zero, 1 subroutine return pointer, 8 for subroutine
parameters, 4 for temporaries, 12 for variables ("called procedure
reserved"), 4 for use by the linker to synthesize 32 bit addresses, 1
frame pointer, and 1 stack pointer.  Floating point instructions and
supervisor mode share these same registers. Internal control
registers are visible in supervisor mode.

On page 77 of the same issue it's suggested (by another author) that
scoreboarding means having a separate set of registers for each
subroutine in order to facilitate task switching.  (-: Does this imply
TMS-9900 compatibility mode? :-)  It would be interesting to learn
whether a single fact gave rise to these strange interpretations.
-- 
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