Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!mailrus!ames!decwrl!hplabs!nsc!stevew
From: stevew@nsc.nsc.com (Steve Wilson)
Newsgroups: comp.arch
Subject: Re: Cretinous status/control register access (Was: Re: 80960 IO)
Keywords: status registers control registers IO chips uarts usarts disk serial
Message-ID: <5136@nsc.nsc.com>
Date: 31 May 88 17:05:55 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <253@babbage.acc.virginia.edu> <1086@mcgill-vision.UUCP> <418@cf-cm.UUCP>
Reply-To: stevew@nsc.UUCP (Steve Wilson)
Organization: National Semiconductor, Sunnyvale
Lines: 25

In article <418@cf-cm.UUCP> mch@computing-maths.cardiff.ac.uk (Major Kano) writes:
>
>   Can anyone out there who designs these things or knows more than I do (not
>difficult :-) say why these abominations exist or if (shock horror !) there is
>actually a good reason for it ?
>

One reason that most software guys are just gonna love is that I/O can be
REAL expensive in hardware designs.  There is usually a single path for
data to exit a given logic module(board or chip), and if you have 27
local registers that are to be R/W, you've got one heck of a data funnel
to create.  This is a favorite place of hardware types(read me here ;-)
to make design trade-offs. 

There really are places in the world where you WANT registers that change
after you have read them.  The best example I know is the common USART data
register.  This guy is going to have a different value everytime a new
character arrives( and depending on the implementation, might actually
change while software is trying to read it(Now I told that software guy
he had to make his interrupt service routine faster ;-) ) 

Steve Wilson
National Semiconductor

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