Path: utzoo!attcan!uunet!mcvax!cernvax!hjm
From: hjm@cernvax.UUCP (hjm)
Newsgroups: comp.arch
Subject: Re: Stack Architectures Can Have Registers
Message-ID: <704@cernvax.UUCP>
Date: 31 May 88 09:04:37 GMT
References: <10076@sol.ARPA>
Reply-To: hjm@cernvax.UUCP (Hubert Matthews)
Organization: CERN European Laboratory for Particle Physics, CH-1211 Geneva, Switzerland
Lines: 21

Stack architectures can, and indeed do, have registers.  Take a look at the
INMOS transputer, for example.  This very nice chip has a three deep stack of
registers and the T800 has 4Kbytes of internal RAM which can be considered to
be 1024 32-bit registers or 4KB of code space, or any mixture of the two (it's
really a sort of software controllable cache).  Stack pushes and pops can be
performed either to external or to internal memory, and the internal ones take
only one cycle at 20 or 30 MHz, whether you're loading a local constant or a
4-bit immediate.

As for the theory that stack-based machines have denser code, then what do you
think of the Transputer's 8-bit instructions which it picks up four at a time?
You can run a 20 MHz T800 with 100ns access time DRAMS if you try very hard 
which is not bad for a 10 MIPS machine.  It even has time to run 8 DMA engines
in parallel with the CPU at this speed.  And no extra wait states either!

Stack-based architectures aren't doomed, they are changing just as fast as the
rest of the world.

	Hubert Matthews

	(...blah, blah, my opinions, blah, blah, ...)