Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!rochester!pt!speech1.cs.cmu.edu!phd From: phd@speech1.cs.cmu.edu (Paul Dietz) Newsgroups: sci.electronics Subject: Re: TTL Questions Message-ID: <1011@speech1.cs.cmu.edu> Date: Sat, 25-Jul-87 02:02:48 EDT Article-I.D.: speech1.1011 Posted: Sat Jul 25 02:02:48 1987 Date-Received: Sat, 25-Jul-87 17:55:58 EDT References: <1395@crash.CTS.COM> <1008@speech1.cs.cmu.edu> <294@uvicctr.UUCP> Distribution: na Organization: Carnegie-Mellon University, CS/RI Lines: 57 Keywords: Arghhhhhhhhhh! In article <294@uvicctr.UUCP> collinge@uvicctr.UUCP (Doug Collinge) writes: >In article <1008@speech1.cs.cmu.edu> phd@speech1.cs.cmu.edu (Paul Dietz) writes: >>In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes: > >>> 2. I've worked with Schottky and Low-power Schottky logic >>>chips in the lab, and have seen that a no connection to inputs, >>>such as a simple AND or OR gate, even sometimes in MUX's and >>>others, drives the input high. Is this guaranteed true? >>Never, never, never, never, never assume this! This is the quickest way >>to get into trouble! Yes, standard TTL floats high by nature, but any >>mild strays are enough to glitch it to another state! > >I read a neato book once by a guy who actually went out and tested things >like this, measured the impedance of wirewrap, found out how many bypass >capacitors you actually need, etc. He said that open TTL inputs WILL NOT >GLITCH even under the most extreme conditions. Remember, before you flame, >he actually made circuits and tried it out... He also pointed out that >you can short one output per package indefinitely for testing purposes >with no harm to the chip - actually pretty handy to know. >-- > Doug Collinge What?! I hate to disagree, but I have gotten burned with REAL, HONEST TO GOODNESS circuits by just this problem. To be exact, I had some D flip- flops that were clearing themselves at random because I had neglected to tie the clear input! Yes this was on a protoboard which certainly adds to the problem, but I still would not sleep nights if I knew I had done this even on a wirewrap board. My old boss used to say that each new designer had to "get burned" before he could really understand that these sorts of things are REAL problems. Maybe 99 times out of 100 you'll get lucky, but eventually, it WILL get you! This stuff about shorting an output sure sounds pretty hokey to me. I guess most (though I doubt all) TTL outputs will survive this, however I doubt you could reasonably expect the rest of the chip to function normally while under this abuse. By the way, did you ever wonder why some static CMOS families have a maximum allowable transition time spec? When switching, there is a usually brief time when the gates are essentially shorting V+ and ground. If you switch too slowly, too much energy must be dissipated, and the part can easily fail. Clearly, shorting the output to the wrong rail is worse. -- Paul H. Dietz ____ ____ Dept. of Electrical and Computer Engineering / oo \ <_<\\\ Carnegie Mellon University /| \/ |\ \\ \\ -------------------------------------------- | | ( ) | | | ||\\ "If God had meant for penguins to fly, -->--<-- / / |\\\ / he would have given them wings." _________^__^_________/ / / \\\\- -- Paul H. Dietz ____ ____ Dept. of Electrical and Computer Engineering / oo \ <_<\\\ Carnegie Mellon University /| \/ |\ \\ \\ -------------------------------------------- | | ( ) | | | ||\\ "If God had meant for penguins to fly, -->--<-- / / |\\\ / he would have given them wings." _________^__^_________/ / / \\\\-