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From: roy@phri.UUCP (Roy Smith)
Newsgroups: comp.unix.wizards,comp.arch
Subject: *Why* do modern machines mostly have 8-bit bytes?
Message-ID: <2807@phri.UUCP>
Date: Tue, 21-Jul-87 11:30:36 EDT
Article-I.D.: phri.2807
Posted: Tue Jul 21 11:30:36 1987
Date-Received: Thu, 23-Jul-87 05:35:28 EDT
References: <142700010@tiger.UUCP> <2792@phri.UUCP> <8315@utzoo.UUCP>
Reply-To: roy@phri.UUCP (Roy Smith)
Organization: Public Health Research Inst. (NY, NY)
Lines: 28
Xref: mnetor comp.unix.wizards:3342 comp.arch:1651
Original-Subject: Re: Size of SysV "block" (really: byte != 8 bits)


In article <8315@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
> Another example worth mentioning is the BBN C/70 and its kin, which have
> 10-bit bytes as I recall.

	Two related questions, now that I've pontificated enough on the
byte != 8 bits issue.

	First, why did older machines have all sorts of strange word
lengths -- 12, 36, and 60 being sizes that I know of, but I'm sure there
were others.

	Second (sort of the inverse of question #1), why do modern machines
have such a strong trend towards having power-of-2 word and byte lengths?
Other than holding ASCII characters nicely and making shift counts fit
nicely, I don't see any real strong reason.  In fact, to really make ASCII
fit nicely, you would want a 7-bit byte size, and if RISC is really the
wave of the future, I would expect to see multiple-shift instructions fall
by the wayside.  Nothing magic about power-of-2 bus widths.

	Anybody for a bit-aligned processor with variable word size (in the
same way the pdp-10 had variable byte size)?  You could do "ADD X, Y, I"
where X and Y are the operands and I is the number of bits of precision
wanted.  I should really mark that with a :-), but I'm partly serious (a
small part).
-- 
Roy Smith, {allegra,cmcl2,philabs}!phri!roy
System Administrator, Public Health Research Institute
455 First Avenue, New York, NY 10016