Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!uunet!pcrat!rick From: rick@pcrat.UUCP (Rick Richardson) Newsgroups: comp.sys.intel,comp.sys.ibm.pc,comp.unix.xenix Subject: Re: 32-bit memory benchmark results for Inboard 386/AT card Message-ID: <361@pcrat.UUCP> Date: Mon, 6-Jul-87 19:07:24 EDT Article-I.D.: pcrat.361 Posted: Mon Jul 6 19:07:24 1987 Date-Received: Tue, 7-Jul-87 07:29:08 EDT References: <122@spdcc.COM> <1176@bobkat.UUCP> <52@b.gp.cs.cmu.edu> Organization: PC Research, Inc., Tinton Falls, NJ Lines: 24 Summary: Depends on compiler/processor Xref: mnetor comp.sys.intel:295 comp.sys.ibm.pc:5380 comp.unix.xenix:447 In article <52@b.gp.cs.cmu.edu>, ralf@b.gp.cs.cmu.edu (Ralf Brown) writes: > In article <1176@bobkat.UUCP> m5@bobkat.UUCP (Mike McNally (Man from Mars)) writes: > >Why is the with-register-variables time for the 32-bit version *slower* > >than the without-register-variables time? Isn't that sort-of strange? > No, its not strange when you consider that Dhrystone is not register- > intensive. > The time savings for access to a register variable may be > as little as three or four clock cycles (depending on wait states), while > pushing and popping take 8 to 10 clocks (again, dep on wait states). Thus, > if the register variable is accessed less than four times, you have a net > increase in execution time. This is all highly compiler/processor dependant, of course. The original published Dhrystone was in Ada, and when I did the translation, I added the register decl's. Naturally, they are (were) optimized for the compiler/processor I was using at the time: an 8088 running Venix 2.0. I'm embarrassed to say that the choices I made and implementation I used were not far-sighted enough to avoid anamolies such as the above. Luckily, compilers are getting smart enough in reg allocation to cover my mistakes! not very -- Rick Richardson, President, PC Research, Inc. (201) 542-3734 (voice, nights) OR (201) 834-1378 (voice, days) seismo!uunet!pcrat!ri<26