Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!rochester!ken From: ken@rochester.arpa (Ken Yap) Newsgroups: sci.electronics Subject: Re: TTL Questions Message-ID: <764@sol.ARPA> Date: Fri, 24-Jul-87 16:41:33 EDT Article-I.D.: sol.764 Posted: Fri Jul 24 16:41:33 1987 Date-Received: Sat, 25-Jul-87 15:16:35 EDT References: <1395@crash.CTS.COM> <1008@speech1.cs.cmu.edu> <294@uvicctr.UUCP> Reply-To: ken@rochester.UUCP (Ken Yap) Distribution: na Organization: U of Rochester, CS Dept, Rochester, NY Lines: 17 |I read a neato book once by a guy who actually went out and tested things |like this, measured the impedance of wirewrap, found out how many bypass |capacitors you actually need, etc. He said that open TTL inputs WILL NOT |GLITCH even under the most extreme conditions. Remember, before you flame, |he actually made circuits and tried it out... He also pointed out that |you can short one output per package indefinitely for testing purposes |with no harm to the chip - actually pretty handy to know. That is comforting to know, but I see no reason to tempt fate unnecessarily. One easy way of dealing with spare inputs on N/AND, N/OR gates is to tie them in parallel to another input. As opposed to pulling them high with a resistor to +5V. Provided you stay within the load capacity of the driving gate. CMOS inputs should not be allowed to float, of course. Ken