Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!utcsri!uthub!thomson From: thomson@uthub.UUCP Newsgroups: comp.arch Subject: Re: Phys vs Virtual Addr Caches Message-ID: <540@uthub.toronto.edu> Date: Mon, 20-Jul-87 12:49:05 EDT Article-I.D.: uthub.540 Posted: Mon Jul 20 12:49:05 1987 Date-Received: Tue, 21-Jul-87 01:00:46 EDT References: <3904@spool.WISC.EDU> <2798@phri.UUCP> Reply-To: thomson@uthub.UUCP (Brian Thomson) Organization: CSRI, University of Toronto Lines: 20 In article <2798@phri.UUCP> roy@phri.UUCP (Roy Smith) writes: > The scheme Larry describes sure sounds like it would be a win but >for one problem. How do you deal with invalidating cache lines when some >DMA I/O device writes into the corresponding main memory location? The I/O >device is generating physical addresses but the cache is keying on virtual >addresses. These IOs were presumably scheduled by software, and the software presumably knows where the device write was directed, so there should be no difficulty in having the processor(s) do a software invalidate of the appropriate virtual addresses once the IOs complete. Note that the transient inconsistency between completion of a device write to a location and the (possibly much) later software invalidation does not pose a problem, since the software will already be structured such that those locations are not read until the IO operation terminates. -- Brian Thomson, CSRI Univ. of Toronto utcsri!uthub!thomson, thomson@hub.toronto.edu