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From: amos@nsta.UUCP (Amos Shapir)
Newsgroups: comp.sys.nsc.32k
Subject: Re: MMU question.
Message-ID: <319@nsta.UUCP>
Date: Sun, 26-Jul-87 01:52:58 EDT
Article-I.D.: nsta.319
Posted: Sun Jul 26 01:52:58 1987
Date-Received: Sun, 26-Jul-87 20:46:19 EDT
References: <14@piring.cwi.nl>
Reply-To: amos%nsta@nsc.com (Amos Shapir)
Distribution: world
Organization: National Semiconductor (Israel) Ltd. Home of the 32532
Lines: 28
Summary: Purge before you leap
Hdate: 29 Tamuz 5747


(I'm posting this to educate other people who may have similar problems)
The  32082 (and  also the  32382) keep  a Translation  Look-aside Buffer
(TLB) in which it looks to find recent translations before searching the
translation  tables; writing  an  address to  the Error/Invalid  Address
(EIA) register  (IVAR on the  32382), and  also changing the  Page Table
Base registers (PTB) purges that address from the TLB.

When changing a mapping of a page  in any table, the best strategy is of
course to make sure that the address  is not used while we change it. If
that is not  possible, we have to guarantee that  no incosistency exists
between the address  kept in the TLB  and that in the tables.  The way I
see it (just  off the top of  my head) is: 1. Invalidate  the Page Table
Entry (PTE)  2. Purge that  entry from the  TLB; any references  to that
address should now be caught by the page fault handler and delayed until
we finish  changing it). 3.  Make the  change in the  PTE; 4. Set  it to
valid.

If you interchange  1 and 2 (that  was what the question  was about), as
long as the entry is valid, any  reference to it will just bring it back
into the TLB again.

Unix uses the  former method, i.e. a process is  blocked while its PTE's
are changing, so the exact order of actions is not important.
-- 
	Amos Shapir			(My other cpu is a NS32532)
National Semiconductor (Israel)
6 Maskit st. P.O.B. 3007, Herzlia 46104, Israel  Tel. (972)52-522261
amos%nsta@nsc.com @{hplabs,pyramid,sun,decwrl} 34 48 E / 32 10 N