Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!gatech!bloom-beacon!husc6!cmcl2!beta!hc!ames!oliveb!prs From: prs@oliveb.UUCP (Philip Stephens) Newsgroups: sci.electronics,rec.music.synth Subject: Re: DCO's revisited - an inquiry into hardware implementation Message-ID: <1948@oliveb.UUCP> Date: Fri, 10-Jul-87 16:43:59 EDT Article-I.D.: oliveb.1948 Posted: Fri Jul 10 16:43:59 1987 Date-Received: Sun, 12-Jul-87 12:22:07 EDT References: <235@cogent.UUCP> <999@vaxb.calgary.UUCP> <678@elmgate.UUCP> Reply-To: prs@oliven.UUCP (Philip Stephens) Organization: Olivetti ATC; Cupertino, Ca Lines: 64 Keywords: now for the real work... Xref: mnetor sci.electronics:931 rec.music.synth:1066 In article <678@elmgate.UUCP> mj@elmgate.UUCP (Mark A. Johnson) writes: > > I've been thinking lately about doing digital music > synthesis with a TI 32010 DSP chip. As I understand it, > the 32010 can perform a multiply/accumulate in 160 ns, > and the 32035 can do it in 60! The nice thing about > the 32010 is that they only cost about $10, so it would > be cheap to cascade them. Me too! Not sure which DSP to use, but I have borrowed doc. book from a coworker for the TI chips. Hard to find which commands take more than one cycle, but 16 bit multiply is single cycle in 320- C10, 20, 25. The C10 and 20 have 200 ns cycle (unless there is a faster version than 1986 book lists), and the 32025 can have cycle of 100 ns. (Note that input clock is 4 times faster, and has a maximum of 150 ns in all 3 cases). Correction, I found the 1 vs 2 cycle info; mostly branches, push/pop, and subroutine stuff take 2; all math is single instruction cycle; there are two table-oriented instructions that take 3 cycles. (I'm looking at the C10 data; the other two don't say cycles but do list word length of instruction, and unlike the C10 they have some 2-word math instructions, which I'm guessing take two cycles). My guess for fetch one of several 32 bit indexes from on-chip ram, add a 16 bit increment, update index, use result as indirect address, and output fetched word to an I/O port (ie, cycles per voice): load word to low accumulator 1 load word to high accumulator 1 add word to low accumulator 1 store word from low accumulator 1 store word from high accumulator 1 load from offchip, with indirect addr 1?? output to port 2 total 8 (or 9?) ie, less than 2 microseconds with the 320C10, < 1 with 20 or C25! (looks like can probably do about 12 voices per C10 at 40 Khz, or more like 8 voices per chip if also do envelopes. Can easily afford two chips, or several. Additional chip(s) for reverb, flanging, etc). I'm just speculating from the data sheet; I hope someone else can give more practical feedback on this or any other DSP chip family (including Motorola, hint hint. And I've sent for OKI info; anyone else already have it? Any other interesting chips to suggest? DSP or other micro processor with fast 16 or 32 bit add and multiply.) Of course, being cheap like the C10 helps!!!!! BTW, you can probably also use the bugger as a UART for MIDI in and out; silly in some applications, but handy if you put it in a gimmick box that is just combining or splitting midi channels, etc. And if you bother to learn to program the 320C10, you might as well use it instead of a Z80 or whatever for simple tasks, even if they waste most of the chip's ability. Why learn 2 or 3 different processors? My idea of efficiency, anyway. Is there enough interest for a DSP or C10 group, or rather, a mailing list? (Email me, and I will report; not sure I want to moderate, but maybe). - Phil prs@oliveb.UUCP (Phil Stephens) or: (hplabs,ihnp4,sun,allegra)oliveb!oliven!prs Mail welcome, but I'm too lazy to always answer 8-} 8-} Work phone: 408 996 3867 x2224 (approx 10a-6p PST/PDT)