Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!rutgers!topaz.rutgers.edu!ron From: ron@topaz.rutgers.edu (Ron Natalie) Newsgroups: comp.arch Subject: Re: What with these Vector's anyways? Message-ID: <13401@topaz.rutgers.edu> Date: Mon, 20-Jul-87 17:04:43 EDT Article-I.D.: topaz.13401 Posted: Mon Jul 20 17:04:43 1987 Date-Received: Wed, 22-Jul-87 00:40:17 EDT References: <218@astra.necisa.oz> <142700010@tiger.UUCP> Organization: Rutgers Univ., New Brunswick, N.J. Lines: 59 Keywords: vector Cray Cyber CDC Cpu Supercomputers > Could someone out there explain to me what the basic idea is behind > supercomputer CPU's? I know what a interrupt vector is (ie an address > pointing to other address) and so forth. But that obviously (or maybe > not?) has nothing to do with the vectors talked of when dealing with > supercomputers. Supercomputers are categorized by being very fast computers. There are various ways of accomplishing this. First you can use rather exotic technology to just get a single CPU (such as you're use to in your VAX) to run a thousand times faster. This of course is very hard, the main problem being that you can't make things small enough so that the propagation of the signals in the wires (no more than the speed of light) doesn't overly slow you down. Well, here comes the tricky parts. What happens if we use a reasonably fast cpu parts in parallel. We ought to be able to get a speed up proportional to the number of parallel parts. There are a couple of ways we can do this. One way is to build our processor to work with arrays in the computations rather than just scalar numbers. One dimensional arrays (vectors) are useful in many calculations. Multidimensioned array calculations can be calculated by multiple vector operations as vector operations can be calculated with multiple scalar operations. Of course, you need to have problems that using an array would be a speed up. This is the ability to being "vectorized" that was referred to. Currently, one needs to figure out how to do this in your source code, but work is underway all over to have compilers find constructs in the code that lend themselves to vectorization and produce the appropriate vector operations. Another way is to replicate the processor so that many operations are done in parallel. One approach is to have a number of processor elements each executing the same program but operating on different pieces of data. This is referred to as SIMD (Single Instruction stream, Multiple Data stream) parallelism. Another approach is to have Mulitiple Instruction and Multiple Data Streams (MIMD) each processor executing its own program with whatever data. To get a MIMD architecture to work, there must be some method of sharing the data. One approach is to all share the same memory (such as with multiple CPU's on the same bus) or to have some form of interprocessor communication between CPU's. Lets look at some popular CPU's CRAY 1 - Vector processor CRAY X-MP - Vector Processor, replicated 1-4 times, shares memory. CRAY 2 - Similar to X-MP, newer and faster technology Denelcor HEP - MIMD parallel, CPU's grouped into PEM's. Each PEM shares data memory, but all PEM's in system share the same data address space. Requests for non-local memory are made and returned through an inter-PEM process switch. NASA MPP (Massively Parallel Processor) - SIMD, on the order of ten thousand CPU data streams. Hypercubes - MIMD, each CPU is interconnected to some number of neighbors as indicated by the edges in a hypercube (the CPU's being at the vertices). -Ron