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From: mlh@houxl.UUCP
Newsgroups: comp.arch,comp.sys.m68k
Subject: Re: Dynamic Ram Controller Chip
Message-ID: <1060@houxl.UUCP>
Date: Thu, 11-Dec-86 22:46:30 EST
Article-I.D.: houxl.1060
Posted: Thu Dec 11 22:46:30 1986
Date-Received: Mon, 15-Dec-86 05:39:06 EST
References: <7720@gatech.EDU>
Organization: AT&T Bell Laboratories, Holmdel
Lines: 30
Keywords: 1M-bit rams, 68030, "pretranslation"
Xref: watmath comp.arch:131 comp.sys.m68k:82

In article <7720@gatech.EDU>, jeff@gatech.EDU (Jeff Lee) writes:
> I was cruising through my WE32100 chip set data sheets and noticed the
> WE32103 DRAM Controller. The sales sheet looked interesting so I started
> going through my data sheet that went with it. At least according to the
> data sheets, it looks pretty good.
          .
          .
          .
> This looks like a great chip to couple with a 68030 and 64 1Mbit chips for
> a small, fast system. Does anyone know if real silicon exists for this thing
> or was it announced ahead of time?

Not only available for some time now, but being used by a number
of customers, both with the AT&T WE 32100 CPU and with 68020's.
Soon to be available at 20+ MHz to complement our WE 32200.

A few more neat features:
- Hook two 32103s up to a single DRAM bank and implement a
  "cheap-and-dirty" dual-port RAM.
- If your system generates dual and quad word READs (get two or four
  words back for each address generated), the 32103 will support.
- Programmable refresh and access times, you can plug in faster
  DRAMs and decrease memory access time under software control.

Datasheets are available by calling (800) 372-2447

			Marc Harrison
			AT&T, Holmdel, N.J.
			(201) 949-1779
			...!ihnp4!houxl!mlh