Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!rutgers!sri-unix!hplabs!hpcea!hpda!hpscda!hprndlb!clw From: clw@hprndlb.HP (Carl Wuebker) Newsgroups: comp.lsi Subject: Re: how does layout affect threshold matching? Message-ID: <5280001@hprndlb.HP> Date: Thu, 25-Dec-86 20:20:53 EST Article-I.D.: hprndlb.5280001 Posted: Thu Dec 25 20:20:53 1986 Date-Received: Sat, 27-Dec-86 06:35:31 EST References: <8612081545.AA05779@vlsi.caltech.edu> Organization: HP Roseville Networks Division Lines: 15 In matching, its a good idea to add some factor (.3, thru .5u to the minimum gate dimensions so linewidth variations don't have as much effect on your circuit. So, for example, if your design rules specify a 3.5u long minimum gate length, go for a x/4. In addition, we've found in our NMOS process that it makes sense not to mirror the FETs -- this is because we connect to the gate with a poly trace on one side (sometimes). A 'wash' which goes in the gate direction can lengthen the gate on one of the mirrored pair and shorten it on the other... Good luck in your MOSIS project! Thanks, Carl Wuebker * {hpfcla|hplabs}!hprndlb!clw * Roseville Networks *