Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!lll-crg!mordor!sri-spam!ames!ucbcad!ucbvax!decvax!linus!philabs!sbcs!nyit!speck@VLSI.CALTECH.EDU (Don Speck) From: speck@VLSI.CALTECH.EDU (Don Speck) Newsgroups: comp.lsi Subject: how does layout affect threshold matching? Message-ID: <355@nyit.UUCP> Date: Wed, 10-Dec-86 17:29:44 EST Article-I.D.: nyit.355 Posted: Wed Dec 10 17:29:44 1986 Date-Received: Sun, 14-Dec-86 14:56:50 EST Sender: aca@nyit.UUCP Organization: NYIT Computer Graphics Lab., Old Westbury, N.Y. Lines: 28 There are times when one desires closely matched enhancement thresholds - in sense amps, current mirrors, op amps, etc. What sorts of things can one do in the layout to minimize threshold differences? Obviously, the transistors should be the same size (to minimize length and width dependence) even under misalignment, and obviously they should have the same number and kind of bends. Do right-angle bends worsen the threshold variation? I try to avoid them on general principle, but sometimes space is tight. Will mirror-image or rotated transistors match as well as transistors sharing a common orientation? Does it help to make the transistors large, in hopes that the threshold variations will average out? Do I need to draw them long, or is it just the total gate area that matters? Does the area/shape of the drain diffusion affect the threshold? This tends to vary under misalignment. Which polarity of transistor matches better, n or p, the one built in the well, or the one built in the substrate? Usually it's impossible to follow all the recommendations at once, so which effects are significant and which aren't? Don Speck speck@vlsi.caltech.edu {seismo,rutgers,ames}!cit-vax!speck