Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/13/84; site intelca.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!houxm!vax135!cornell!uw-beaver!tektronix!zehntel!zinfandel!vlsvax1!qantel!intelca!clif
From: clif@intelca.UUCP (Clif Purkiser)
Newsgroups: net.micro,net.arch
Subject: 386 Architectural Description
Message-ID: <130@intelca.UUCP>
Date: Wed, 23-Oct-85 14:48:30 EST
Article-I.D.: intelca.130
Posted: Wed Oct 23 14:48:30 1985
Date-Received: Mon, 28-Oct-85 03:56:03 EST
Distribution: net
Organization: Intel, Santa Clara, Ca.
Lines: 199
Xref: watmath net.micro:12516 net.arch:1956

At the request of some people I am reposting a fairly brief description
of the architecture of the 80386.  


                          80386 Product Brief



Introduction

The 80386 is a high performance, 32-bit microprocessor designed for 
advanced applications like CAD/CAM engineering workstations, high 
resolution graphics, and factory automation.  The 80386 brings to 
these application an unprecedented performance of 3-4 million 
instructions per second, complete 32-bit architecture, and paged 
virtual memory support.  The iAPX 386 family of products provides the 
lastest in microprocessor technology and performance without 
compromising compatibility to the large software base of the iAPX 86 
family.  Of special interest is the 80386's unique virtual machine 
capabilities which allow multitasking between diverse operating 
systems such as Unix and MS-DOS.  This allows OEM's to incorporate 
large amounts of standard 16-bit application software directly into 
new 32-bit designs.


HIGHLIGHTS

o   32-bit virtual memory microprocessor with 4 gigabytes physical  
    address space, 4 gigabyte maximum segment size, and 64 terabyte 
    virtual address space.

o   Sustained performance of 3-to-4 million instructions per second 
    (MIPS)

o   Flexible 32-bit architecture with 8-, 16-, 32-bit data types.

o   Memory management and protection with segmentation and paging 
    integrated on-chip.

o   32 entry on-chip paging cache (translation lookaside buffer) with 
    a 98% hit rate for efficient paging

o   Object-code compatible with all iAPX 86 family processors

o   Virtual 8086 mode allows direct execution of iAPX 86 family 
    software and operating systems as guest in a protected 32-bit 
    environment.

o   High speed interface for 80287 and 80387 floating point numeric 
    coprocessors

o   Demultiplexed 32-bit address and data bus with 32 megabyte per 
    second bandwidth for high speed local buses or local caching

o   High speed, high density, CHMOS III technology yields 12 and 16 
    MHz clock rates



DESCRIPTION

The 80386 rivals the performance of most super minicomputers, at 16 
MHz, the 80386 is capable of executing at sustained rates of 3-to-4 
million 32-bit instructions per second.  This achievement was made 
possible through a state-of-the-art design combining advanced 
semiconductor technology, a pipelined architecture, address 
translation caches, a high performance bus, and specialized, 
high-speed coprocessors.

The 80386 32-bit processor provides a rich, generalized register and 
instruction set for manipulating 32-bit data and addresses.  Advanced 
features, such as scaled indexing and a 64-bit barrel shifter, ensure 
efficient addressing and fast instruction processing.

For the convenience of compiler writers, the 80386 provides multiple 
addressing modes, a capability which ensures that high-level languages 
can be implemented in the most efficient manner possible.  Scaling by 
data type is supported for direct indexing of arrays without the need 
to perform math explicitly on an effective address.

The 80386 instruction set is marked by both power and flexibility.  It 
offers the compiler writer and assembly language programmer a broad 
range of choices in which operations and data can be specified.  
Special emphasis has been placed on providing optimized instructions 
for high-level languages and operating system functions.  Programmers 
will find that the instruction set is suitable for the entire spectrum 
of high-performance computer applications from engineering 
workstations through commercial data processing and real-time 
control.  Instructions are clear, consistent, and quickly learned.  
The same highly efficient code is easily generated from source 
languages as varied as C, Fortran, Cobol, and Ada*.

Advanced functions, such as hardware-supported multitasking and 
virtual memory support, provide the foundation necessary to build the 
most sophisticated multitasking and multiuser systems.  Many operating 
system functions have been placed in hardware to enhance execution 
speed.  The integrated memory management and protection mechanism 
translates virtual addresses to physical addresses and enforces the 
protection rules necessary for maintaining task integrity in a 
multitasking environment.

The 80386 provides easy access to the large base of software developed 
for the 8086, 8088, 80186, 80188, and 80286 microprocessors.  
Binary-level-code compatibility allows execution of existing 16-bit 
applications without recompilation or reassembly, directly in a 
virtual iAPX 86 environment.  Programs and even entire operating 
systems written for iAPX 86 processors can be run as guests under new 
32-bit 80386 operating systems.  Since the 80386 memory management 
unit is a superset of the 80286's, all 80286 software including 
operating systems is directly portable to the 80386.  The OEM 
preserves his software investment and can reduce the time-to-market 
for new products.




PIPELINED MICROARCHITECTURE

The 80386's pipelined architecture performs instruction fetching, 
decoding, execution, and memory management functions in parallel.  
With this highly parallel operation, instruction fetch and decode 
times disappear as consumers of execution time, allowing performance 
levels 5 times greater than non-pipelined implementations.


ON-CHIP MEMORY MANAGEMENT AND PROTECTION

The 80386 provides efficent support for memory management and demand 
paged virtual memory on-chip.  By performing memory management 
on-chip, the 386 eliminates the serious access delays inherent in 
other implementations that use off-chip memory management units.  The 
benefit is not only high performance but relaxed memory-access time 
requirements, hence lower system cost.


HIGH SPEED BUS

The 80386 has seperate 32-bit data and address paths.  A 32-bit access 
can be completed in only two clock cycles, enabling the bus to sustain 
a throughput of 32 Megabytes per second.  By making prompt transfers 
between the microprocessor, memory, and peripherals, the high-speed 
bus design ensures that the entire system benefits from the 
processor's increased performance.


CHMOS III

Intel's advanced CHMOS III process (Complementary High Speed Metal 
Oxide Semiconductor) eliminates the frequency and reliability 
limitations of traditional CMOS processes and opens a new era in 
microprocessor performance.  It combines the high performance and high 
density capabilities of Intel's leading HMOS III technology with the 
low power characteristics of CMOS.  Using this technology, the 80386 
is designed to operate at 12 and 16 MHz.


NUMERIC COPROCESSOR SUPPORT

The 80287 and 80387 are high-performance floating-point coprocessors 
for 80386 designs.  A coprocessor takes numerics functions that would 
normally be performed in software by the microprocessor and instead 
executes them in hardware.  The 80287 makes numerics power available 
to low-cost 80386 designs, while the 80387 provides enhanced 
functionality and the highest numerics performance available for 
32-bit microprocessors.  Both implement the IEEE 754 floating point 
standard, with high-precision 80-bit architectures and full support 
for single, double, and extended precision operations.  Both 
coprocessors offer substantial performance enhancements over numeric 
software implementations, are binary-compatible with the 
industry-standard 8087 numerics coprocessor, and are fully supported 
by Intel and third-party high-level languages.


COPROCESSORS

Most applications can obtain an even higher boost in performance by using 
specialized coprocessors.  A coprocessor takes functions that would 
normally be performed in software by the microprocessor and instead 
executes them in hardware.  Coprocessors are best viewed as a means of 
extending the iAPX 386's already extensive instruction set.  Instructions 
for the coprocessors are located in-line with code for the processor.

For applications that would benefit from higher precision integer and 
floating point calculations, Intel will offer the 80387, a numerics 
coprocessor with full support for the IEEE standard for floating-point 
operations.  The 80387 will run more than six times faster than the 80287, 
which has already set new standards in numerics performance, and is 
software compatible with its predecessor the 8087.  The iAPX 386's 
coproccessor interface supports both the 80287 and the 80387 to offer the 
system designer the choice of low cost or high performance numeric 
solutions.

For word processing and other common applications, system performance will 
benefit by using text and graphics coprocessors, and for systems connected 
by local area networks, the 82586 and 82588 LAN coprocessors speed 
interprocessor communication.

Clif Purkiser
{hplaps quantal amd}!intelca!clif