Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84 / ST 1.0; site saber.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!nsc!saber!msc From: msc@saber.UUCP (Mark Callow) Newsgroups: net.micro,net.arch Subject: Re: Re: 386 Family Products Message-ID: <1857@saber.UUCP> Date: Thu, 7-Nov-85 19:52:39 EST Article-I.D.: saber.1857 Posted: Thu Nov 7 19:52:39 1985 Date-Received: Sun, 10-Nov-85 06:46:56 EST References: <129@intelca.UUCP> <392@aum.UUCP> <625@spar.UUCP> <391@sesame.UUCP> <7475@watdaisy.UUCP> <259@well.UUCP> Distribution: net Organization: Saber Technology, San Jose, CA Lines: 16 Xref: watmath net.micro:12627 net.arch:2050 J. R. (May the farce be with you) Stoner, Esq. writes > In actual fact National Semiconductor has removed the breakpointing registers > from the 32082 after CPU step K was released. Wrong. The latest 32032 CPU rev is H. The latest 32082 MMU rev is M. The errata (excuuse me, "User Information") sheet for the Rev M 32082, dated 8th August 1985, says that "physical breakpoints cannot be used reliably". However the part definitely still contains two breakpoint registers. -- From the TARDIS of Mark Callow msc@saber.UUCP, sun!saber!msc@decwrl.dec.com ...{decwrl,ucbvax}!sun!saber!msc, ...{amdcad,ihnp4}!saber!msc