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From: bobp@petfe.UUCP (Dan Masi)
Newsgroups: net.arch
Subject: Re: 386 Architectural Description
Message-ID: <531@petfe.UUCP>
Date: Mon, 28-Oct-85 11:19:52 EST
Article-I.D.: petfe.531
Posted: Mon Oct 28 11:19:52 1985
Date-Received: Wed, 30-Oct-85 04:20:37 EST
Organization: Perkin-Elmer DSG, Tinton Falls, N.J.
Lines: 16


<<>>

>   32 entry on-chip paging cache (translation lookaside buffer) with 
>   a 98% hit rate for efficient paging
>     ^^^^^^^^^^^^

Does this mean that I will see a 98% cache hit rate for *all* programs
that I can run on this processor???   Hmmm...


Dan Masi
...!petsd!petfe!bobp