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Path: utzoo!linus!philabs!cmcl2!harvard!seismo!hao!noao!terak!doug
From: doug@terak.UUCP (Doug Pardee)
Newsgroups: net.arch
Subject: Re: 386 Architectural Description
Message-ID: <847@terak.UUCP>
Date: Mon, 4-Nov-85 14:37:26 EST
Article-I.D.: terak.847
Posted: Mon Nov  4 14:37:26 1985
Date-Received: Fri, 8-Nov-85 03:59:24 EST
References: <531@petfe.UUCP> <2343@ukma.UUCP> <3786@dartvax.UUCP>
Organization: Calcomp Display Products Division, Scottsdale, AZ, USA
Lines: 16

> >   32 entry on-chip paging cache (translation lookaside buffer) with 
> >   a 98% hit rate for efficient paging
>
> I think such an outrageous claim needs considerable documentation.  Usually
> people only claim 50-75% cache hit rates.

This isn't a data cache, it's a paging/MMU cache.  National Semi has
claimed a 98% hit rate for the 32-entry MMU TLB in their NS32081, and
my experience has been that this is a valid figure, at least when
running 4.2BSD.

Since the 32081 has 512-byte pages, the cache addresses 16K.  I hear
that the '386 has 4K pages, so the cache addresses 128K, and a hit
rate of even 99% would seem reasonable.
-- 
Doug Pardee -- CalComp -- {calcom1,savax,seismo,decvax,ihnp4}!terak!doug