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Path: utzoo!watmath!watnot!watdaisy!lmpopp
From: lmpopp@watdaisy.UUCP (Len Popp)
Newsgroups: net.micro,net.arch
Subject: Re: Re: 386 Family Products
Message-ID: <7475@watdaisy.UUCP>
Date: Mon, 4-Nov-85 10:32:07 EST
Article-I.D.: watdaisy.7475
Posted: Mon Nov  4 10:32:07 1985
Date-Received: Tue, 5-Nov-85 22:31:05 EST
References: <129@intelca.UUCP> <392@aum.UUCP> <625@spar.UUCP> <391@sesame.UUCP>
Reply-To: lmpopp@watdaisy.UUCP (Len Popp)
Distribution: net
Organization: U of Waterloo, Ontario
Lines: 18
Keywords: hardware breakpoint register
Xref: watmath net.micro:12574 net.arch:2011
Summary: 

In article <391@sesame.UUCP> slerner@sesame.UUCP (Simcha-Yitzchak Lerner) writes:
><>
>
>For those who haven't received their '386 info packets yet, a nice
>feature that I wish all chips would include:
>
>4 hardware breakpoint registers!!

The 32000 family MMU (32082, I think) has had this feature for a couple of
years.  There are two registers with breakpoint addresses and conditions.
A breakpoint can be triggered on execution, read or write of the virtual or
physical address.  There is also a count register specifying the number of
breakpoints to ignore before breaking.

A nice feature, yes, but not a groundbreaking innovation.

		Len Popp
		lmpopp@watdaisy