Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site peora.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!vax135!petsd!peora!jer From: jer@peora.UUCP (J. Eric Roskos) Newsgroups: net.arch Subject: Re: 386 Architectural Description Message-ID: <1771@peora.UUCP> Date: Mon, 4-Nov-85 09:03:02 EST Article-I.D.: peora.1771 Posted: Mon Nov 4 09:03:02 1985 Date-Received: Tue, 5-Nov-85 09:29:23 EST References: <531@petfe.UUCP> <5671@amdcad.UUCP> Organization: Perkin-Elmer SDC, Orlando, Fl. Lines: 12 > This is a paging cache, not an instruction or data cache. That is, > instead of poking through the page tables for each virtual address > generated by the program, you cache the virtual to physical address > mapping for 32 pages. This saves a lot of time. Does the 386 let you invalidate entries in the paging cache from outside? -- Shyy-Anzr: J. Eric Roskos UUCP: Ofc: ..!{decvax,ucbvax,ihnp4}!vax135!petsd!peora!jer Home: ..!{decvax,ucbvax,ihnp4}!vax135!petsd!peora!jerpc!jer US Mail: MS 795; Perkin-Elmer SDC; 2486 Sand Lake Road, Orlando, FL 32809-7642