Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84 / ST 1.0; site saber.UUCP Path: utzoo!watmath!clyde!cbosgd!ihnp4!nsc!saber!msc From: msc@saber.UUCP (Mark Callow) Newsgroups: net.micro,net.arch Subject: Re: Re: 386 Family Products (32K Breakpoint Registers) Message-ID: <1862@saber.UUCP> Date: Mon, 11-Nov-85 15:43:49 EST Article-I.D.: saber.1862 Posted: Mon Nov 11 15:43:49 1985 Date-Received: Wed, 13-Nov-85 07:30:07 EST References: <129@intelca.UUCP> <392@aum.UUCP> <625@spar.UUCP> Distribution: net Organization: Saber Technology, San Jose, CA Lines: 21 Xref: watmath net.micro:12673 net.arch:2077 > From the TARDIS of Mark Callow: > >J. R. (May the farce be with you) Stoner, Esq. writes > >> In actual fact National Semiconductor has removed the breakpointing registers > >> from the 32082 after CPU step K was released. > > > >Wrong. > > > >The latest 32032 CPU rev is H. > > True, but the 320*16* CPU rev K was released some time ago. I suspect that > is what J. R. was referring to. They made it to rev N on that part before > it more-or-less stabilized. He may have had the 32016 in mind. However, the breakpoint registers are in the 32082 MMU (as he said) and they haven't been removed from the current rev M part. The only support required of the CPU is the NMI trap which is unlikely to go away. Therefore the CPU rev is irrelevant to this discussion. -- From the TARDIS of Mark Callow msc@saber.UUCP, sun!saber!msc@decwrl.dec.com ...{decwrl,ucbvax}!sun!saber!msc, ...{amdcad,ihnp4}!saber!msc