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Path: utzoo!linus!decvax!ittatc!dcdwest!sdcsvax!sdcrdcf!trwrb!scgvaxd!felix!birtch!Oleg Kiselev (OLG)
From: Oleg Kiselev@birtch.UUCP (OLG)
Newsgroups: net.arch
Subject: Re: 386 Architectural Description
Message-ID: <82@birtch.UUCP>
Date: Thu, 31-Oct-85 17:38:53 EST
Article-I.D.: birtch.82
Posted: Thu Oct 31 17:38:53 1985
Date-Received: Sun, 3-Nov-85 15:10:06 EST
References: <531@petfe.UUCP>
Organization: Birtcher, Santa Ana, Ca.
Lines: 21

In article <531@petfe.UUCP> bobp@petfe.UUCP (Dan Masi) writes:
>>   32 entry on-chip paging cache (translation lookaside buffer) with 
>>   a 98% hit rate for efficient paging
>>     ^^^^^^^^^^^^
>Does this mean that I will see a 98% cache hit rate for *all* programs
>that I can run on this processor???   Hmmm...

According to 386 specs, translation buffer maps 128K worth of 4K pages.
Most small programs written for 8086/80286 systems had a 64K data segment 
(limit for most programmers who did not want to pay speed penalties for address
decoding). For those programs 98% hit rate is quite reasonable. 

I guess 386 was tested running MS-DOS... Some habits never go away ....:-)

-- 
Disclamer: My employers go to church every Sunday, listen to Country music,
and donate money to GOP. I am just a deviant.
----------------------------------+ Don't bother, I'll find the door,
"Only through a violent revolution|                       Oleg Kiselev.
 can the existing order be pre-   |...!{trwrb|scgvaxd}!felix!birtch!oleg
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