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From: jer@peora.UUCP (J. Eric Roskos)
Newsgroups: net.arch
Subject: Re: 386 Architectural Description
Message-ID: <1771@peora.UUCP>
Date: Mon, 4-Nov-85 09:03:02 EST
Article-I.D.: peora.1771
Posted: Mon Nov  4 09:03:02 1985
Date-Received: Tue, 5-Nov-85 09:29:23 EST
References: <531@petfe.UUCP> <5671@amdcad.UUCP>
Organization: Perkin-Elmer SDC, Orlando, Fl.
Lines: 12

> This is a paging cache, not an instruction or data cache. That is,
> instead of poking through the page tables for each virtual address
> generated by the program, you cache the virtual to physical address
> mapping for 32 pages. This saves a lot of time.

Does the 386 let you invalidate entries in the paging cache from outside?
-- 
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