Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site unc.unc.UUCP Path: utzoo!watmath!clyde!bonnie!akgua!mcnc!unc!omondi From: omondi@unc.UUCP (Amos Omondi) Newsgroups: net.arch Subject: Re: 386 Architectural Description Message-ID: <507@unc.unc.UUCP> Date: Sun, 3-Nov-85 13:23:45 EST Article-I.D.: unc.507 Posted: Sun Nov 3 13:23:45 1985 Date-Received: Sun, 10-Nov-85 06:29:36 EST References: <531@petfe.UUCP> <2343@ukma.UUCP> <3786@dartvax.UUCP> Organization: CS Dept, U. of N. Carolina, Chapel Hill Lines: 26 > > >> 32 entry on-chip paging cache (translation lookaside buffer) with > > >> a 98% hit rate for efficient paging > > >> ^^^^^^^^^^^^ > > > > > >Does this mean that I will see a 98% cache hit rate for *all* programs > > >that I can run on this processor??? Hmmm... > > > > I think this flame is unwarranted. If the author had read the original > > posting more closely, he would have noticed that it was a brief des- > > cription of the 386, and if he would have bothered to read some more > > detailed literature from Intel, he would have found out that this fi- > > gure of 98% is for typical systems. > > What is a "typical system"? I think this is a completely warranted flame. > I think such an outrageous claim needs considerable documentation. Usually > people only claim 50-75% cache hit rates. > > chuck@dartvax The figure of 98 % is not really outrageous. As Phil Ngai points out the writer is giving figures for the number of entries in the address translation hardware where 16 to 64 entries will usually give a hit ratio of anywhere from 90% to 99%. Actually i wonder if there are any machines out there with a translation cache of more than 64 entires.