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From: sambo@ukma.UUCP (Father of micro-ln)
Newsgroups: net.arch
Subject: Re: 386 info
Message-ID: <2359@ukma.UUCP>
Date: Mon, 4-Nov-85 20:05:57 EST
Article-I.D.: ukma.2359
Posted: Mon Nov  4 20:05:57 1985
Date-Received: Tue, 5-Nov-85 09:48:19 EST
References: <965@mcnc.mcnc.UUCP>
Reply-To: sambo@ukma.UUCP (Father of micro-ln)
Distribution: net
Organization: Univ. of KY Mathematical Sciences
Lines: 30

In article <965@mcnc.mcnc.UUCP> jnw@mcnc.UUCP (John White) writes:
>The registers ax,bx,cx,dx,si,di,sp,bp have been expanded to 32 bits
>(called eax,ebx ...). Each of these registers has its own set of
>capabilities (as with the 86). (This means that for a given amount of
>effort writing an optimizing compiler, code for a clean arcitecture
>like the 68020 will be better optimized than for the 386.)

If I understand the literature correctly, each task has a default of
either 16- or 32-bit operands and addresses.  The former would allow
for emulating the 286, for example.  The default can be overridden by
a special prefix, which affects only the next instruction.  Anyway,
if the default is set for 32-bit operands and addresses, all of a sud-
den there are also quite a few more addressing options, so that the
registers are almost truly general purpose.  For example, it is possi-
ble to multiply any two registers.  (Actually, this particular capabi-
lity is available even if it is set up for the 16-bit default.)  It is
also possible to use just about any register as an index register.  (I
think SP is the only register that can't be used this way - it remains
almost exclusively as a stack pointer.)  So it should be a lot easier
to write an optimizing compiler - the only thing is that to use use
these additional addressing options usually lengthens the instruction
by an extra byte.
--
Samuel A. Figueroa, Dept. of CS, Univ. of KY, Lexington, KY  40506-0027
ARPA: ukma!sambo<@ANL-MCS>, or sambo%ukma.uucp@anl-mcs.arpa,
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	"Micro-ln is great, if only people would start using it."