Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site dartvax.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!ihnp4!ucbvax!decvax!dartvax!chuck From: chuck@dartvax.UUCP (Chuck Simmons) Newsgroups: net.arch Subject: Re: 386 Architectural Description Message-ID: <3786@dartvax.UUCP> Date: Fri, 1-Nov-85 04:17:14 EST Article-I.D.: dartvax.3786 Posted: Fri Nov 1 04:17:14 1985 Date-Received: Sun, 3-Nov-85 06:29:27 EST References: <531@petfe.UUCP> <2343@ukma.UUCP> Organization: Dartmouth College, Hanover, NH Lines: 18 > >> 32 entry on-chip paging cache (translation lookaside buffer) with > >> a 98% hit rate for efficient paging > >> ^^^^^^^^^^^^ > > > >Does this mean that I will see a 98% cache hit rate for *all* programs > >that I can run on this processor??? Hmmm... > > I think this flame is unwarranted. If the author had read the original > posting more closely, he would have noticed that it was a brief des- > cription of the 386, and if he would have bothered to read some more > detailed literature from Intel, he would have found out that this fi- > gure of 98% is for typical systems. What is a "typical system"? I think this is a completely warranted flame. I think such an outrageous claim needs considerable documentation. Usually people only claim 50-75% cache hit rates. chuck@dartvax