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From: ken@turtlevax.UUCP (Ken Turkowski)
Newsgroups: net.arch,net.micro.68k
Subject: Re: Asynchronous State machines
Message-ID: <935@turtlevax.UUCP>
Date: Thu, 24-Oct-85 04:20:26 EDT
Article-I.D.: turtleva.935
Posted: Thu Oct 24 04:20:26 1985
Date-Received: Sat, 26-Oct-85 04:03:49 EDT
References: <389@aum.UUCP>
Reply-To: ken@turtlevax.UUCP (Ken Turkowski)
Followup-To: net.arch
Distribution: net
Organization: CADLINC, Inc. @ Menlo Park, CA
Lines: 30
Xref: watmath net.arch:1943 net.micro.68k:1260

In article <389@aum.UUCP> freed@aum.UUCP (Erik Freed) writes:
>I have received some mail requesting further info on Asyncronous state
>machines. I wish that there were some great book on it that I could
>give a pointer to, but I don't know of one. There are some papers such as
>
>	DIRECT IMPLEMENTATION OF ASYNCHRONOUS CONTROL UNITS
>	      Lee A. Hollaar Jan 12 1982
>	      University of Utah
>	      IEEE transactions on Computing 1982
>
>I am not sure how you would get a reprint though.
>
>       The basic topic is covered  (I think) by most textbooks on logic.
>It is simply the use of Asynchronous logic to make a finite state machine.
>The hard part is solving the problem of Hazards or race conditions. These
>are not a problem in syncronous designs. One way of getting around this is
>to keep your state transitions dependant on only one input signal(at a time).
> ...

I don't know what this is doing in net.micro.68k, so I took the liberty
of redirecting all followups into net.arch only.

The one signal that can be used is one such as the SYNC signal
that is used on all asynchronous buses to validate the address
on the bus.  Once the data has been written or gated onto the bus,
an ACK signal is passed back to acknowledge the transfer.
-- 
Ken Turkowski @ (CADLINC --> CIMLINC), Menlo Park, CA
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