Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site aum.UUCP Path: utzoo!linus!decvax!decwrl!Glacier!well!ptsfa!aum!freed From: freed@aum.UUCP (Erik Freed) Newsgroups: net.arch,net.micro.68k Subject: Re: Asynchronous State machines Message-ID: <395@aum.UUCP> Date: Mon, 28-Oct-85 18:40:16 EST Article-I.D.: aum.395 Posted: Mon Oct 28 18:40:16 1985 Date-Received: Fri, 1-Nov-85 00:18:54 EST References: <389@aum.UUCP> <6077@utzoo.UUCP> Organization: The Aurora Systems Bunch Lines: 35 Xref: linus net.arch:1769 net.micro.68k:1209 > > Lots of the designs I see are done in slow sync ways and they > > could be done in faster and smaller async circuitry. My point is that most > > engineers would rather plug in a sequencer than a delay line and in alot of > > the cases this is a big lose. Once you get used to them they are a blast > > to use. > > One possible reason for the preference for sequencers is that sequencer > timing tolerances can be made quite tight, where delay lines usually have > fairly sloppy specs. I know this is why I gave up on delay lines for > timing dynamic RAMs -- if you believe in worst-case design, the delay > lines' loose tolerances slow things down seriously. I admit to not being > an expert in this area, so perhaps there is something I missed, but all > the delay-line specs I saw had an awful lot of +- in them. > -- > Henry Spencer @ U of Toronto Zoology > {allegra,ihnp4,linus,decvax}!utzoo!henry I don't think that you got the point, Async circuitry wins in many places. The lack of syncronizing being one of the major ones. The relatively small amount of min/max skew in delay lines seems rather dwarfed by these advantages. I mean we are talking at least 100 -200 ns for the sync problem alone. Try looking at say a 16R8 versus a 16L8 PAl with the non-registered version you only have to worry about the skew *BETWEEN* prop times on a single pal. This allows some very creative fast designs. For the registered version you have to wait the maximum prop and clock_to_output times. This makes async machines have much smaller states. and no granularity you get from a master clock. Signals change when they are ready, not when the clock is ready. I used to feel exactly the same way, but as I got into them I found that I was finding extra time all over the place. Try it you'lle like it! -- ------------------------------------------------------------------------------- Erik James Freed Aurora Systems San Francisco, CA {dual,ptsfa}!aum!freed