Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site petfe.UUCP Path: utzoo!watmath!clyde!cbosgd!ihnp4!houxm!vax135!petsd!petfe!bobp From: bobp@petfe.UUCP (Dan Masi) Newsgroups: net.arch Subject: Re: 386 Architectural Description Message-ID: <531@petfe.UUCP> Date: Mon, 28-Oct-85 11:19:52 EST Article-I.D.: petfe.531 Posted: Mon Oct 28 11:19:52 1985 Date-Received: Wed, 30-Oct-85 04:20:37 EST Organization: Perkin-Elmer DSG, Tinton Falls, N.J. Lines: 16 <<>> > 32 entry on-chip paging cache (translation lookaside buffer) with > a 98% hit rate for efficient paging > ^^^^^^^^^^^^ Does this mean that I will see a 98% cache hit rate for *all* programs that I can run on this processor??? Hmmm... Dan Masi ...!petsd!petfe!bobp