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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: 386 info
Message-ID: <222@mips.UUCP>
Date: Tue, 12-Nov-85 00:39:55 EST
Article-I.D.: mips.222
Posted: Tue Nov 12 00:39:55 1985
Date-Received: Wed, 13-Nov-85 08:31:17 EST
References: <965@mcnc.mcnc.UUCP> <830@x.UUCP>
Distribution: net
Organization: MIPS Computer Systems, Mountain View, CA
Lines: 30

Bob Mabee writes:
> In article <965@mcnc.mcnc.UUCP> jnw@mcnc.UUCP (John White) writes:
> (summarizing Intel release on the new 386)
> >First, if all 32 entries in the cache
> >are used, then one must be freed up. As the access and dirty bits may have
> >been changed, the entry must be written back to the page table.
> 
> This is a bug (or misquoted).  The accessed and dirty bits have to be written
> back to memory immediately they are set, using a bus-lock read-alter-rewrite

Must be misquoted.  WHen the chip decides it needs to change one of these
bits, it reissues the request (with bus-lock), sets the bit, writes it back.
One certainly doesn't want the TLB to have a different idea of these bits
than those kept in memory, not only for the reasons above, but because:
	1) you need at least 1 more bit of state per entry in the TLB, to
	note whether or not the entry has changed.
	2) Even worse, you have to keep track of where the TLB entry CAME
	FROM, so you can write it back, which adds a lot more state per entry.
	(If N is size of cache, you need N physical addresses, whereas the
	way the chip works uses exactly 1).
Changes from non-referenced to referenced don't happen very often;
changes from clean to dirty hardly ever happen, at least measured on the
scale of TLB translations.  An excellent analysis of TLB behavior is:
Douglas Clark, Joel Emer, "Performance of the VAX-11/780 Translation
Buffer: Simulation and Measurement", ACM Trans on COmp Syst 3, 1(Feb 85), 31-62.
-- 
-john mashey
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