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From: phil@amdcad.UUCP (Phil Ngai)
Newsgroups: net.arch
Subject: Re: 386 Architectural Description
Message-ID: <5671@amdcad.UUCP>
Date: Sat, 2-Nov-85 00:28:04 EST
Article-I.D.: amdcad.5671
Posted: Sat Nov  2 00:28:04 1985
Date-Received: Sun, 3-Nov-85 06:27:43 EST
References: <531@petfe.UUCP>
Reply-To: phil@amdcad.UUCP (Phil Ngai)
Organization: AMD, Sunnyvale, California
Lines: 26

In article <531@petfe.UUCP> bobp@petfe.UUCP (Dan Masi) writes:
>>   32 entry on-chip paging cache (translation lookaside buffer) with 
>>   a 98% hit rate for efficient paging
>
>Does this mean that I will see a 98% cache hit rate for *all* programs
>that I can run on this processor???   Hmmm...

This is a paging cache, not an instruction or data cache. That is,
instead of poking through the page tables for each virtual address
generated by the program, you cache the virtual to physical address
mapping for 32 pages. This saves a lot of time. With 32 4K pages
mapped, that's 128K and 98% doesn't sound unreasonable. Let's look at
it another way, suppose you only use each address (assume 32 bit
words) in a 4K page once and after that demanded a new page. Then your
hit rate on a 1 entry TLB is 1023 out of 1024 accesses or about 99.9%.

You probably were thinking of a data cache. But that's not what Intel
said. Hey Intel, why don't you defend yourselves? Are you going to sit
there and wait for your competitors to defend you? :-)
-- 
 The Miami Police Department's Vice Squad has an annual budget of $1.5M.
 Each episode of the TV show "Miami Vice" costs $1.6M.

 Phil Ngai +1 408 749-5720
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