Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site well.UUCP Path: utzoo!linus!philabs!cmcl2!seismo!lll-crg!well!asgard From: asgard@well.UUCP (J. R. Stoner) Newsgroups: net.micro,net.arch Subject: Re: Re: 386 Family Products Message-ID: <259@well.UUCP> Date: Wed, 6-Nov-85 22:51:02 EST Article-I.D.: well.259 Posted: Wed Nov 6 22:51:02 1985 Date-Received: Sat, 9-Nov-85 04:59:43 EST References: <129@intelca.UUCP> <392@aum.UUCP> <625@spar.UUCP> <391@sesame.UUCP> <7475@watdaisy.UUCP> Reply-To: asgard@well.UUCP (J. R. Stoner) Distribution: net Organization: Whole Earth 'Lectronic Link, Sausalito, CA Lines: 21 Keywords: hardware breakpoint register Xref: linus net.micro:11407 net.arch:1853 In article <7475@watdaisy.UUCP> lmpopp@watdaisy.UUCP (Len Popp) writes: >> >>For those who haven't received their '386 info packets yet, a nice >>feature that I wish all chips would include: >> >>4 hardware breakpoint registers!! > >The 32000 family MMU (32082, I think) has had this feature for a couple of >years. There are two registers with breakpoint addresses and conditions. >A breakpoint can be triggered on execution, read or write of the virtual or >physical address. There is also a count register specifying the number of >breakpoints to ignore before breaking. In actual fact National Semiconductor has removed the breakpointing registers from the 32082 after CPU step K was released. -- From the mania of: J. R. (May the farce be with you) Stoner, Esq.