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From: sarwono@puff.UUCP
Newsgroups: net.micro.68k,net.micro.16k
Subject: Re: Re: Bus Error Effluvia
Message-ID: <440@puff.UUCP>
Date: Fri, 27-Sep-85 12:18:43 EDT
Article-I.D.: puff.440
Posted: Fri Sep 27 12:18:43 1985
Date-Received: Mon, 30-Sep-85 00:55:03 EDT
Organization: U of Wisconsin CS Dept
Lines: 38
Xref: watmath net.micro.68k:1163 net.micro.16k:392

> My initial thought about this was "who cares if the processor doesn't backtrack
> and redo the instructions after returning from the bus error," but after
> thinking about it for a little while, I can think of at least two problems
> that this might cause.
> 
> 1) Since the processor can't get out onto the bus if it is busy either waiting
> 	for ready or a bus error, one wouldn't think that it could corrupt
> 	anything that is not recoverable.  However, it can fiddle around
> 	with its internal state all it wants to.  Now, if one of the things
> 	that it does internally is muck with some registers (a completely
> 	valid thing to do) that would get changed as a result of the trap
> 	handler, we have a problem, I would think.  This seems real special
> 	case, though I do remember that at least some early versions of
> 	4BSD paid attention to how register variables were allocated by the
> 	c compiler, and used this information when mixing assembly with
> 	c code...
> 
> 2) In the same tack, I think that if Mot ever includes a data cache on their
> 	chip, they will have to pay special attention to the amount of
> 	concurrency they allow for data accesses on both the external bus
> 	and the internal cache bus.
> 
> So what do y'all think?  Does anyone know exactly what the thing tosses on the
> bus, and whether it is possible for the trap handler to modify the return
> state such as to change the results of half-executed instructions
> (or whole executed instructions after the bus-error write)?
> -- 
> ...and I'm sure it wouldn't interest anybody outside of a small circle
> of friends...
> 
> Ken Shoemaker, Microprocessor Design for a large, Silicon Valley firm
> 
> {pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds
> 	
> ---the above views are personal.  They may not represent those of the
> 	employer of its submitter.

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