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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: Re: Cache Revisited
Message-ID: <193@mips.UUCP>
Date: Thu, 19-Sep-85 21:30:49 EDT
Article-I.D.: mips.193
Posted: Thu Sep 19 21:30:49 1985
Date-Received: Sat, 21-Sep-85 11:48:37 EDT
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Pat Caudill writes:
> 	If you have read the article on the IBM 801 project this was just
> what they did. The cache was the register set (which was medium large -
> 32 registers). But there was a very very smart compiler which optimized
> register usage even across subroutine calls. Go look at the article it
> was published in a SIGPLAN several years ago.
The referenced reference is:
M. Auslander, M. Hopkins, "An Overview of the PL.8 Compiler", Proc. SIGPLAN
Symp. Compiler Construction, ACM, Boston, June 1982, 22-31.
A useful related article is:
F. Chow, J. L. Hennessy, "Register Allocation by Priority-Based Coloring",
Proc. SIGPLAN Symp. Compiler Construction, ACM, Montreal, June  1984, 222-232.
-- 
-john mashey
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