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From: jer@peora.UUCP (J. Eric Roskos)
Newsgroups: net.arch
Subject: Re: Tagged architectures
Message-ID: <1683@peora.UUCP>
Date: Fri, 27-Sep-85 08:02:28 EDT
Article-I.D.: peora.1683
Posted: Fri Sep 27 08:02:28 1985
Date-Received: Sun, 29-Sep-85 08:30:39 EDT
References: <796@kuling.UUCP> <1713@orca.UUCP> <1599@peora.UUCP> <335@ihlpl.UUCP> <2384@uvacs.UUCP> <412@ucsfcca.UUCP> <926@loral.UUCP>
Organization: Perkin-Elmer SDC, Orlando, Fl.
Lines: 19

> And with a tagged memory system, you must read a memory word before
> doing a write (to see if the tag allows writing).  This causes alot of
> extra memory accesses and thus detracts from the performance achievable.

No, it only makes it more expensive.  There are always* RAM parts available
that are faster than those used for the main memory; it's just a question
of whether you want to incur the extra cost.  (For some kinds of tag bits,
if you can manufacture your own parts, it's also possible to implement
unconventional RAMs that reduce the number of accesses required; e.g.,
RAMs that can sense a bit transition when you write to them can be used to
implement particular kinds of test & set-style tags.)

*Well, unless you have memory cycle times in the ones of nanoseconds.
-- 
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