Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84 SMI; site sun.uucp Path: utzoo!linus!philabs!cmcl2!seismo!harvard!talcott!panda!genrad!decvax!decwrl!sun!guy From: guy@sun.uucp (Guy Harris) Newsgroups: net.micro.68k,net.micro.16k Subject: Re: PDP11s vs the micros Message-ID: <2572@sun.uucp> Date: Thu, 8-Aug-85 00:58:41 EDT Article-I.D.: sun.2572 Posted: Thu Aug 8 00:58:41 1985 Date-Received: Sun, 11-Aug-85 06:35:39 EDT References: <1617@hao.UUCP> <847@mako.UUCP> <2422@sun.uucp> Organization: Sun Microsystems, Inc. Lines: 55 Xref: linus net.micro.68k:984 net.micro.16k:330 > The "p-machine" garbage for the 32xxx was probably just early marketing > hype. Which means "but it's not a general register machine, it's a p-machine!" isn't a legitimate reason why the 32xxx's SP, etc. aren't general registers - which is what the person replying to John Gilmore said. (There may be legitimate reasons, but "it's a p-machine" isn't one of them - because it isn't a p-machine.) > As for eliminating auto +/- addressing mode, I support that decision. Not knowing what the exact tradeoffs were, I neither support it nor oppose it. The P6/32 doesn't have auto-I/D except on the SP, and it seems not to have suffered *too* much in performance :-) (~4-7x 11/780 isn't too bad, especially for a TTL machine with an instruction set which a fair fraction of the VAX's complexity). It may also be easier to do pipelining if fewer of the addressing modes have side-effects - you don't have to worry about the (r4)+ two pipeline stages behind screwing up your movl r4,(or, if you have multiple copies of the general register set, having to worry about propagating the change from the auto-increment to the instruction-unit copy of r4 forward to the execution-unit copy at the right time). > Given their decision to "back out" instructions that get page faults > rather than dump out the internal microstate like the 68010, National > would have to keep shadow copies of too much internal stuff around in > case a page fault came through. Well, maybe. Returning to the original topic, as described by the subject - the PDP-11 can only modify a maximum of two registers during the operand preparation, so some models have (or have what amounted to) a register which remmbered the register numbers of the two registers modified and the amount added to or subtracted from them. When you take a fault, the fault handler saves the contents of this register (which, presumably, freezes until read) and uses it to back up the faulting instruction. (This backup could also be mostly simulated in software - see the routine "backup" in the assembler language support code for UNIX on PDP-11s lacking this register - 11/40, 11/34, 11/23, 11/60...). > I think having full memory to memory addressing is more useful that auto > +/-, especially for compiler generated code. (well maybe not for pcc -- > it's model seems to be put something in a register, munch on it, put it > back in memory). Well, if the RISC people are correct, neither of them are necessarily useful. One problem with having auto-I/D modes is you set up your language to use them; then, when you compile code turned for machines with auto-I/D on machines which don't have it, you get code that's not as good as would be generated by a more straightforward coding. Also, at least if you use things like "+=", I think PCC will make use of memory-to-memory modes in simple expressions; if the expression is more complicated, it's probably faster to do it in a register anyway. Guy Harris