Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: Notesfiles $Revision: 1.7.0.8 $; site uiucdcs Path: utzoo!linus!philabs!cmcl2!seismo!lll-crg!dual!qantel!ihnp4!inuxc!pur-ee!uiucdcs!bcase From: bcase@uiucdcs.Uiuc.ARPA Newsgroups: net.arch Subject: Re: RISC and MIPS Message-ID: <27800052@uiucdcs> Date: Wed, 7-Aug-85 11:31:00 EDT Article-I.D.: uiucdcs.27800052 Posted: Wed Aug 7 11:31:00 1985 Date-Received: Mon, 12-Aug-85 04:20:18 EDT References: <419@kontron.UUCP> Lines: 29 Nf-ID: #R:kontron.UUCP:-41900:uiucdcs:27800052:000:1758 Nf-From: uiucdcs.Uiuc.ARPA!bcase Aug 7 10:31:00 1985 /* Written 7:28 am Aug 6, 1985 by hammond@petrus.UUCP in uiucdcs:net.arch */ Anyway, the RISC claims will always be slightly dubious to me until I actually see a machine performing as claimed in a real situation. Hidden gotchas have a way of getting missed in paper exercises. /* End of text from uiucdcs:net.arch */ You probably won't have to wait TOO long since Acorn computer co. of England just announced (in Electronics magazine) that they have good, working die, the first time, after only 18 months of effort by 4 people. The machine is able to sustain 3 of its MIPS and running real programs (code produced by compilers) was "about 2 times a VAX 11/780" and 10 times an IBM PC-AT. The article did not mention anything about memory management, so they may or may not be winning because of the lack of translation. Anyway, they will be selling an evaluation board for $2000 (which contains 1 MByte of memory, the processor and some bootstrap ROM) which plugs into the $400 Acorn 6502-based micro- computer. Thus for about $3000, a person can get a really nice personal workstation, and what performance. Oh, the board comes with a BCPL compiler and a MODULA-2 compiler, a small operating system, and a window-oriented text editor. More software is on the way (C, Pascal, etc.). It is true that this RISC will have about the same performance as the 68020, but this RISC is fabricated with MUCH less aggressive technology, and when shrunk to modern design rules, will probably be significantly faster than more complex 32-bitters (the minor cycle time of a 68020 is 60 ns. (at 16.67 MHz) while the minor cycle time of this RISC is 150 ns.). True, we should not count our RISCs before they are hatched, but there are real advanteges to RISC.