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Path: utzoo!linus!philabs!cmcl2!seismo!utah-cs!schimpf
From: schimpf@utah-cs.UUCP (James Schimpf)
Newsgroups: net.micro
Subject: Use of timers on INTEL 80186
Message-ID: <3437@utah-cs.UUCP>
Date: Thu, 8-Aug-85 21:47:23 EDT
Article-I.D.: utah-cs.3437
Posted: Thu Aug  8 21:47:23 1985
Date-Received: Sun, 11-Aug-85 07:16:12 EDT
References: <542@brl-tgr.ARPA>
Reply-To: schimpf@utah-cs.UUCP (James schimpf)
Organization: Univ of Utah CS Dept
Lines: 47
Keywords: 80186,INTEL
Summary: 80186 Timer use Secrets ?



	We are building a small system here based on an INTEL 80186
and are trying to use one of the on chip timers to generate a baud
rate clock.  The '186 is running at 8 MHz (16 MHz crystal) and we
are trying to use TIMER 0 on the chip as the generator for a x16
clock for a 9600 baud serial line.

	Our processor registers (TIMER, DMA, memory control etc.)
are mapped to memory starting at F0000H.  Our code does the
following:

		Set location F0052H (Timer 0 A register) to 0DH
		Set location F0056H (Timer 0 cntl)       to C001H

and a continuous ~150Khz clock is generated.  

	The above is pretty much a copy of what is done in the INTEL
application note AP 186.  It does work ONCE. It will continue to run
for hours this way but after the chip is warmed up if it is RESET or
powered down and back up again this timer won't work again.  Also at
this point (i.e. timer not working) the only count value that will
make it work is a 1 in the TIMER A register.  Using this you can
generate a 4 MHz clock signal.  From the design notes on the chip
this frequency is impossible (2 MHz max with a 8 MHz clock).

	Ah ha, you say its a bad chip ! Well no, we have exactly the
same problem on 4 different chips (2 B step chips and 2 C step chips).
(The B & C stuff means something to the INTEL folk)

	The processors all seem to run OK as the above messing with
timer registers is all done via a monitor/debugger running using the
chip.  And this debugger never stops or even gliches during the
testing. 

        We have read the manuals and the AP note so we think we are
doing the right thing but is there some secret to this ?  That we
can make them work when the chip is cold shows we are doing some of
the right stuff but is there something else ?

	Any suggestions or war stories would be appreciated.  Mail
it to me or put it on the net if you think it is of general
interest.

--Jim Schimpf U. of U. CS Dept
  ARPA:     schimpf@utah-20
  Net Mail: {ihnp4,decvax,seismol!utah-cs!schimpf