Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/5/84; site othervax.UUCP Path: utzoo!watmath!clyde!bonnie!akgua!whuxlm!harpo!decvax!linus!philabs!micomvax!othervax!ray From: ray@othervax.UUCP (Raymond D. Dunn) Newsgroups: net.micro Subject: Re: EPROM memory lifetime query Message-ID: <687@othervax.UUCP> Date: Thu, 22-Aug-85 11:58:31 EDT Article-I.D.: othervax.687 Posted: Thu Aug 22 11:58:31 1985 Date-Received: Sun, 25-Aug-85 02:44:06 EDT References: <562@wdl1.UUCP> <1686@hao.UUCP> <1043@mtgzz.UUCP> Reply-To: ray@othervax.UUCP (Raymond D. Dunn) Followup-To: net.micro Organization: Philips Information Systems - St. Laurent P.Q., Canada Lines: 48 Summary: In article <1043@mtgzz.UUCP> dmt@mtgzz.UUCP (d.m.tutelman) writes: >> > How long do current EPROMS and EEPROMS hold their memory? >> Intel states (in their EPROM Applications Manual AFN-01648A) that you will >> have 5% cell failures after only 220,000 years at 70C in storage. This is >> from tests taken at high temperatures to accelerate failures. Assuming that ^^^^^^^^ >> these failures are linear over time gives a cell failure rate of 0.0001% ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >> in 4.4 years at 70 degrees C. >> ... >> {ucbvax!hplabs | allegra!nbires | harpo!seismo } !hao!hull > >Thanks, Howard. I really enjoyed your response. >Just to put a number on it that's meaningful to me, I used your data >to get a failure rate per chip. Assuming a 128K chip (current >state-of-the-industry), with the failure of any bit meaning the >chip has failed, I get an annual failure rate of 2%. >Put another way, the MTBF of the chip is about 50 years. >... > Dave Tutelman ...ihnp4!mtuxo!mtgzz!dmt Hey! Lets take a look at this... Assuming that your *computation* of the figures is correct, (and its too early in the morning for me to delve into probability calculation (:-)), are you interpreting the figures correctly? We are talking about electron leakage from the cells here, so that surely you *cannot* assume linearity. As a (made up example), if we assume that the initial charge on all cells is between 90 and 100% of their maximum, and that they will fail if the charge drops below 40%, then we have to wait for leakage to drop the cells by 50% before *any* cell fails. Now even if the leakage from each cell is at a different rate, we still have a non-linear failure rate. Anyway, how does the rate of loss of cell info compare with the failure rate of the chip itself? I would have thought that the chance of the chip failing outright was several orders of magnitude higher than the probability of getting decayed info from the chip. Some knowledgable comment would be appreciated. (A small flame here - please do not post a response to a request for information if you only *think* you know the answer (as many did to the original request), this only confuses the issue - flame off). Ray Dunn ..philabs!micomvax!othervax