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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <163@mips.UUCP>
Date: Sat, 10-Aug-85 18:28:22 EDT
Article-I.D.: mips.163
Posted: Sat Aug 10 18:28:22 1985
Date-Received: Mon, 12-Aug-85 23:14:39 EDT
References: <419@kontron.UUCP> <27800052@uiucdcs>
Organization: MIPS Computer Systems, Mountain View, CA
Lines: 32

> 
>> Anyway, the RISC claims will always be slightly dubious to me until I
>> actually see a machine performing as claimed in a real situation.
>> Hidden gotchas have a way of getting missed in paper exercises.
>> /* End of text from uiucdcs:net.arch */
> 
> You probably won't have to wait TOO long since Acorn computer co. of
> England just announced (in Electronics magazine) that they have good,
> working die, the first time, after only 18 months of effort by 4
> people.  The machine is able to sustain 3 of its MIPS and running
> real programs (code produced by compilers) was "about 2 times a VAX
> 11/780" and 10 times an IBM PC-AT.  The article did not mention anything
> about memory management, so they may or may not be winning because of
> the lack of translation.....
> ....  True, we should not count our
> RISCs before they are hatched, but there are real advanteges to RISC.

1) Real advantages to RISC : yes.
2) lack of memory management: unless one is just interested in a point
product with a fairly narrow performance range, one must be exceedingly
careful in memory management design for RISC, or you rapidly discover
that you get a chip OK for controllers or unprotected systems, and
near-useless for reasonable multi-tasking operating systems.
3) (Opinion, perhaps quite biased): it's pretty easy to do a RISC that's
2X a 780.  What's harder, but necessary, is to figure out how the same
chip architecture gets you to 5X, and soon 10X in a reasonable way;
just running the clock faster doesn't do it.
-- 
-john mashey
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