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From: eugene@ames.UUCP (Eugene Miya)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <1093@ames.UUCP>
Date: Mon, 19-Aug-85 12:33:02 EDT
Article-I.D.: ames.1093
Posted: Mon Aug 19 12:33:02 1985
Date-Received: Sat, 24-Aug-85 13:28:27 EDT
References: <419@kontron.UUCP> <2300001@uicsl>
Organization: NASA-Ames Research Center, Mtn. View, CA
Lines: 28

I have been following this discussion for some time.  So what's the
bottom line?  If architecture is your thing, the proof of the putting
are going to be running systems.  The critics of RICS then focus their
attack on a definition of MIPS.  We've had two (or more) "What is a
MIP letter?" in addition to the original one.

A couple of years ago just before the Winter Usenix conference, I saw the
Massively Parallel Processor (MPP).  It is rated at peak speed of 16
billion instructions per second (16 GIPS).  Now they only add later that this
is an 8-bit word with 1-bit serial data paths.  It burns me up when recently
I saw a television ad that Goodyear Aerospace did this `great' thing
for NASA at the cost of 10 million dollars. {oops, sorry, got out of
hand, flame off}

A problem is, certainly, how we measure things.  One letter brought out
the need to define what an instruction was.  The letter did not specifically
mention a property by name: that was `atomicity.'  Another problem is
a common base set of units: is there an appropriate conversion factor of
a 64-bit instruction to an 8-bit?  Is a factor of 8 good enough, probably
not.  Let's keep "standards" out of the discussion for now, and explore this
a bit.  Whetstones were mentioned in another letter, but the only people
who use these are computer manufacturers.  [MGT]FLOPS are another gastly
measure.  What qualities do our performance metrics need to have?

--eugene miya
  NASA Ames Research Center
  {hplabs,ihnp4,dual,hao,decwrl,allegra}!ames!aurora!eugene
  emiya@ames-vmsb