Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site oakhill.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!allegra!mit-eddie!think!harvard!seismo!ut-sally!oakhill!davet
From: davet@oakhill.UUCP (Dave Trissel)
Newsgroups: net.micro.68k
Subject: Latest MC68020 bug list by request
Message-ID: <483@oakhill.UUCP>
Date: Thu, 15-Aug-85 22:51:18 EDT
Article-I.D.: oakhill.483
Posted: Thu Aug 15 22:51:18 1985
Date-Received: Mon, 19-Aug-85 08:43:30 EDT
Organization: Motorola Inc. Austin, Tx
Lines: 57

[]

In article 190@sri-unix.ARPA (Victor R. Frank) said:

>  In article (338@oakhill.UUCP) Dave Trissel gave the current (Feb 12, 1985)
> bug list for the MC68020, one trivial error concerning the LINK instruction.
>
>     I read in the August-September 1985 issue of Micro Cornucopia
>on page 50, in an article entitled "The 32-Bit Super Chaps" by 5
>authors from Definicon Systems, allegations that in the 68020:
>
>     1.  The barrel shifter does not work,
>     2.  The co-processor interface does not work,
>     3.  The data sheet AC characteristics cannot be met.
>
>   ...     but I would be interested in seeing on the net
>(net.micro.68k) a rebuttal from Motorola, and any current
>information of bugs/availability of the 68881 floating point unit.

I guess Definicon Systems gets asked quite frequently why they aren't using
the faster MC68020 so they came up with some lame excuses :-).  (I'll give
you one guess as to where they got this info from.)

The allegations are quite absurd. Here is the latest bug list for the '020
1A45J mask which has been out for some time. This is as of August 12, 1985.

  1) the CAS2.x instruction will not operate correctly if either of the
     operand effective addresses is data register indirect (Dn).

  2) The TAS instruction will not operate properly if either the read or write
     portion of the RMC cycle is bus-errored.  (We have a ten line fix for
     this in the exception handler.)

  3) The BTST (bit test) instruction when used as follows will not do the bit
     test:
			 BTST    Dn,#<  >

The first two pertain mostly to OS type semaphore handling and are easily
circumvented.

The third is just discovered a few days ago and is quite interesting.  A few
years ago another guy in my group asked me why you would ever want to
dynamically test a bit in a constant field so I thought up an example.

While investigating this just reported bug we discovered that our assemblers
do not and evidently have never supported this as a valid instruction.  So
it's just possible that it never was even tried by a programmer.

So much for the '020.  The MC68881 FPU has been heavily sampled and is close
to being put into standard production.  There is only one serious bug on that
chip that I am aware of.  One of the log functions has errors (I think logn.)
But the fix is quite trivial since we have a logn(x-1) which works.  So by
including an extra subtract the correct result can be obtained.

 -- Dave Trissel
    Motorola Semiconductor
    Austin, Texas            {ihnp4,seismo}!ut-sally!oakhill!davet