Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site oakhill.UUCP Path: utzoo!linus!philabs!cmcl2!seismo!ut-sally!oakhill!davet From: davet@oakhill.UUCP (Dave Trissel) Newsgroups: net.arch Subject: Re: Cache revisited Message-ID: <484@oakhill.UUCP> Date: Thu, 15-Aug-85 23:50:50 EDT Article-I.D.: oakhill.484 Posted: Thu Aug 15 23:50:50 1985 Date-Received: Mon, 19-Aug-85 20:47:34 EDT References: <5374@fortune.UUCP> <901@loral.UUCP> <2583@sun.uucp> <5459@fortune.UUCP> Reply-To: davet@oakhill.UUCP (Dave Trissel) Distribution: net Organization: Motorola Inc. Austin, Tx Lines: 36 In article <5459@fortune.UUCP> wall@fortune.UUCP (Jim wall) writes: > > Someone in replying tomy original article on cache said that >the hit rate on the internal cache in the 68020 is about 50%. >Anyone care to agree with that? Anyone care to tell me what >reasonable application or operating system spends 50% of its time >in loops that are smaller that 256 bytes?? > The problem is that cache hit values are so variable that it really doesn't make sense to talk about an average figure. The lowest I've seem for the '020 is a range of 10 to 15 percent which was taken from a monitoring of the Unix operating system. (Sorry don't remember which version.) One would suspect that operating systems would be among the worst performers. On the other hand, we have lots of reports ranging from 30 to 65 percent for measured applications. Yet another problem measuring cache hits specifically on the '020 is the fact that since the chip always does a 32-bit longword instruction fetch from the bus, if only the first word is used (e.g. it finishes an earlier instruction or is itself a 16-bit instruction) then the other word is treated as a cache hit. This tends to boost cache hit rate values depending on just what you define a cache hit to be. BTW, the 10 to 15 percent cache hit rate is nothing to sneeze at when you look at real performance gain. Take a hit rate of 10 percent. That 10 percent amounts to a much higher realized performance improvement when you consider that the cached reads would take 1.5 to 2 times longer to do on the external bus and that the 15 to 20 percent less activity of that bus can then be used for simultaneous data reads and writes by the processor. So your real improvement could be anywhere up to 30 percent. -- Dave Trissel Motorola Semiconductor Austin, Texas {ihnp4,seismo}!ut-sally!oakhill!davet