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From: joel@peora.UUCP (Joel Upchurch)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <1432@peora.UUCP>
Date: Mon, 5-Aug-85 09:05:31 EDT
Article-I.D.: peora.1432
Posted: Mon Aug  5 09:05:31 1985
Date-Received: Sat, 10-Aug-85 23:39:17 EDT
References: <419@kontron.UUCP> <237@weitek.UUCP> <437@petrus.UUCP>
Organization: Perkin-Elmer SDC, Orlando, Fl.
Lines: 15

>A side note:  The Berkeley RISC's have no  absolute  addressing  mode,
>they  fake  it by using R0 (always 0) plus an offset.  BUT, the offset
>can only be 13 bits, hence they can only absolutely address the  first
>2**13  locations  in  memory.  Large  programs,  eg  the  UNIX  kernel
>(particularly from Berkeley) use much more than 2**13 (like 2**19) for
>instructions,  hence  the  problem is how well would a RISC do when it
>takes 2 instructions to form an absolute address and probably requires
>a  register?  I'll accept RISCs when I see one runnning 4.3 BSD faster
>than an 11/780.

        I would like to point out that the IBM 370 (usually considered
	a CISC :-> ) doesn't have absolute addressing and that it only
	has a displacement of 2**12 bytes. They seem to be able to get
	some rather large operating systems, including UNIX, to run on
	it.