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From: hammond@petrus.UUCP (Rich A. Hammond)
Newsgroups: net.arch
Subject: Re: RISC and MIPS
Message-ID: <449@petrus.UUCP>
Date: Thu, 8-Aug-85 09:10:00 EDT
Article-I.D.: petrus.449
Posted: Thu Aug  8 09:10:00 1985
Date-Received: Mon, 12-Aug-85 05:43:47 EDT
References: <419@kontron.UUCP> <237@weitek.UUCP> <437@petrus.UUCP> <1028@sdcsvax.UUCP>
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> In article <437@petrus.UUCP> I said
> >[...]  I'll accept RISCs when
> >I see one runnning 4.3 BSD faster than an 11/780.
> 
> Darrell Long replies:
> You should see how much faster our Pyramid runs 4.2 than our 11/780!

1) I'm not sure I'll accept the claim that the Pyamids, ridge, ...
are truly RISC machines, they have taken the overlapping registers idea
and that alone, even on a CISC, gives a great advantage.

2) What I should have said was that I wanted to see a RISC chip running
4.? BSD faster than a VAX.  The claims from UCB about the RISC I & II
were based on simulations which avoided the nasty problems of making
the kernel run.  As I noted before, hidden gotchas have a way of popping
up when you actually try and get something running.  Also, I want a
chip fabricated with the technology used for the M68000 when it came out.
It seems clear that since a 68020 can run faster than a 780 that a RISC
chip made now with leading edge technology should also run faster.

3) The claims that a RISC is better have to be taken with 3 provisions:
  a) Technology is important (i.e. if you need to have 1 memory cycle
     per instruction you'd better have fairly fast memory relative to
     the CPU implementation.  This is the current state, but it may change.
  b) I take a large grain of salt with the claim that RISC was designed
     faster than conventional micros, since a lot of what I suspect is
     complex on other micros is interrupt, trap, supervisor vs non-priv
     support and documentation, none of which the UCB people did much of.
  c) Although UCB claims to have "avoided complications" in their comparisons
     by using the same technology for the compiler (pcc) in comparisons,
     I think they introduced a very serious bias.  The pcc was never
     designed to generate good code and the RISC architecture might simply
     be a better match for pcc than a CISC architecture.  This seems to
     be supported by the CAN article which said that recoding some of the
     benchmarks for the RISC, 68000 and Z8000 in assembly resulted in
     code which was 1/2 the size of the RISC and significantly faster.

In summary, I like the ideas of RISC, I'm not convinced they're the only
way to go, but it was a good area to explore.

Rich Hammond