Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site brl-tgr.ARPA Path: utzoo!watmath!clyde!cbosgd!ihnp4!mhuxn!mhuxr!ulysses!gamma!epsilon!zeta!sabre!petrus!bellcore!decvax!genrad!panda!talcott!harvard!seismo!brl-tgr!tgr!BillW@SU-SCORE.ARPA From: BillW@SU-SCORE.ARPA (William Chops Westfield) Newsgroups: net.micro Subject: Re: Z-80 and DRAMs Message-ID: <937@brl-tgr.ARPA> Date: Fri, 23-Aug-85 18:13:54 EDT Article-I.D.: brl-tgr.937 Posted: Fri Aug 23 18:13:54 1985 Date-Received: Mon, 26-Aug-85 00:51:37 EDT Sender: news@brl-tgr.ARPA Lines: 30 Although 256K and some 64K memorys require 256 refresh cycles, they do not require them as often as rams requiring only 128 cycles. On top of that, the z80 does many more refresh cycles than are actually required (one after EVERY opcode fetch, I think). Therefore, It is a relatively simple matter to add an extra flip flop or two outside of the z80. (well, perhaps not THAT simple, but:) My 1982 TI Memory data book has an applications brief to do exactly this on page 211 entitled "256-cycle refresh conversion". Hmm, I think I can even reproduce it: _____ A7 >-----------------------------------------+ 1 | /--------------\ | OUT+-----> address A7 to mplx | | /--------+0 SEL| | 74ls393 | / \__+__/ 1 of 2 data selector \ _______+________+_ | (eg 74ls157, leftover \ / A B C D A B C D | | mplx unit, etc.) Z80 \ | 1 2 | | signals \ | CLKA CLKB | | |\ \ \____+________+____/ | 74ls04 | \ \ | | | /--+ O-(-----/ from | | | / \------------ Q1D | | |/ | RFSH>----+--------------------------------------/ Enjoy BillW