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From: bcase@uiucdcs.Uiuc.ARPA
Newsgroups: net.arch
Subject: Re: MMU Cache revisited
Message-ID: <27800053@uiucdcs>
Date: Tue, 13-Aug-85 11:58:00 EDT
Article-I.D.: uiucdcs.27800053
Posted: Tue Aug 13 11:58:00 1985
Date-Received: Tue, 20-Aug-85 07:49:25 EDT
References: <2581@sun.uucp>
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Nf-ID: #R:sun.uucp:-258100:uiucdcs:27800053:000:624
Nf-From: uiucdcs.Uiuc.ARPA!bcase    Aug 13 10:58:00 1985


/* Written  7:29 pm  Aug  8, 1985 by gnu@sun.uucp in uiucdcs:net.arch */
/* ---------- "Re: MMU Cache revisited" ---------- */
From the hardware designs I've seen, it's a lot harder to build an MMU
with a cache than it is to build one out of RAM.  This is because
the cache is doing in hardware what would otherwise be done in software
(updating the entries in the hardware translation table).  Whether
/* End of text from uiucdcs:net.arch */

No, an MMU built with a TLB (address translation cache) does not by
definition include hardware reload of translation entries.  Software
reload and a TLB are perfectly compatible.