Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site celerity.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!vax135!cornell!uw-beaver!tektronix!hplabs!sdcrdcf!sdcsvax!celerity!boston From: boston@celerity.UUCP (Boston Office) Newsgroups: net.arch Subject: Re: RISC and MIPS Message-ID: <314@celerity.UUCP> Date: Wed, 14-Aug-85 13:37:29 EDT Article-I.D.: celerity.314 Posted: Wed Aug 14 13:37:29 1985 Date-Received: Tue, 20-Aug-85 20:59:56 EDT References: <419@kontron.UUCP> Reply-To: boston@celerity.UUCP (Boston Office) Distribution: net Organization: Celerity Computing, San Diego, Ca. Lines: 41 Summary: In article <419@kontron.UUCP> steve@kontron.UUCP (Steve McIntosh) writes: >[ From the DTACK newsletter #44 (August 1985) ] > >"RISC ARCHITECTURES: > >WHAT IS A MIP? > >Technically, a MIP is a million instructions per second. OK then, >what's an instruction? Ah! That's a very good question! > >Take, for example, the following 68000 instruction: > > MOVE.W D7,(A3)+ > >That instruction stores the lower word of the 32-bit register D7 at the >address contained in the 32-bit address register A3, and then >increments A3 by two (two bytes = one word). Here is that instruction's >equivalent for the Nat Semi 32016: > > MOVW D7,(SB) > ADDQD 2,SB > >The same operation in a hypothetical RISC machine: > > MOVE R7,(R#) > LOAD 2,R4 > ADD R4,R# > >For simplicity, suppose that those three computers each performed that >equivalent instruction (or instruction sequence) in exactly one >microsecond. Then the 68000 would be operating at 1 MIP, the 32000 >series at 2 MIPS, and the hypothetical RISC machine at 3 MIPS. > >EACH COMPUTER WOULD BE PERFORMING EXACTLY THE SAME AMOUNT OF WORK! > ... PRECISELY! That is why, when evaluating a system's power, we need standards apart from the individual architecture. Ask for Whetstone MIPS if you seek a general raw-power figure, or other benchmarks that more reflect your need. (When Celerity quotes MIPS, for example, we quote whetstone MIPS - even within a RISC-like architecture.)