Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site brl-tgr.ARPA
Path: utzoo!watmath!clyde!burl!ulysses!allegra!mit-eddie!think!harvard!seismo!brl-tgr!tgr!cottrell@nbs-vms.ARPA
From: cottrell@nbs-vms.ARPA
Newsgroups: net.lang.c
Subject: Split I & D
Message-ID: <871@brl-tgr.ARPA>
Date: Wed, 21-Aug-85 18:47:37 EDT
Article-I.D.: brl-tgr.871
Posted: Wed Aug 21 18:47:37 1985
Date-Received: Sat, 24-Aug-85 17:25:22 EDT
Sender: news@brl-tgr.ARPA
Lines: 21

/*
> > [general Intel segmented architecture flame]	<<-- ME
> > I mean nobody seriously suggests a dual 
> > model for the pdp-11/70 (16 bits for small model/22 bits for large )-:
> 
> I heartily agree, but remember there are 2 memory models on the PDP-11.
> Ever hear of split I&D?
> -- 
> 	Peter da Silva (the mad Australian)
     `
Touche! Almost. Here it's just a question of degree, of how much space
your code & data use. The compiler just generates `.data' & `.text'
directives and lets the chips fall where they may. No memory management.
It's the loader that supports the split I&D spaces. 

	jim		cottrell@nbs

The opinions expressed are mine. If they are not yours, why don't you
just go kill yourself & quit taking up space on my planet :-)
*/
------