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From: ken@turtlevax.UUCP (Ken Turkowski)
Newsgroups: net.micro.68k,net.arch
Subject: Re: Re: x86/68x buses
Message-ID: <808@turtlevax.UUCP>
Date: Tue, 2-Jul-85 02:43:18 EDT
Article-I.D.: turtleva.808
Posted: Tue Jul  2 02:43:18 1985
Date-Received: Wed, 3-Jul-85 20:06:37 EDT
References: <344@osu-eddie.UUCP> <600@intelca.UUCP> <2275@sun.uucp> <611@intelca.UUCP> <2306@sun.uucp> <9@intelca.UUCP>
Reply-To: ken@turtlevax.UUCP (Ken Turkowski)
Organization: CADLINC, Inc. @ Menlo Park, CA
Lines: 29
Xref: watmath net.micro.68k:979 net.arch:1517
Summary: 

In article <9@intelca.UUCP> kds@intelca.UUCP (Ken Shoemaker) writes:
>> I think the 68020 drives the address of prefetches (if there's not
>> already a cycle on the bus) but will not assert address strobe if it
>> hits the cache.  AS doesn't come out until the addresses are stable
>> anyway, so the cache lookup is overlapped with the address driver
>> propagation delay (and setup time on whoever's receiving the
>> addresses).  Serious MMUs start to translate the address before AS
>> anyway, so it actually helps to not have to latch the address, since
>
>regardless of the timing of the address strobe, you really can't start
>looking up addresses for either your cache, or for your MMU until the
>addresses are guaranteed stable on the address bus, or have I missed
>some major advance in non-deterministic logic?

What you have missed is a sense of timing.  The address to the on-chip
cache is stable 50 nS or so before the address on the bus.  There are
two sets of drivers between the two:  one set on chip to driver the
outside world, and the other to buffer the addresses to devices off the
board.  There's probably at least 25 nS for each of them.  On top of
that, mosts busses require some amount of setup time before the address
strobe, something like another 50 nS.  So here we have 100 nS between
the time when addresses to the cache are stable to the time when the
address strobe is to be asserted.

-- 

Ken Turkowski @ CADLINC, Menlo Park, CA
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