Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site sdcsvax.UUCP Path: utzoo!watmath!clyde!cbosgd!ihnp4!mhuxn!mhuxr!mhuxt!houxm!mtuxo!mtunh!mtung!mtunf!ariel!vax135!timeinc!phri!pesnta!amd!amdcad!decwrl!decvax!ittvax!dcdwest!sdcsvax!darrell From: darrell@sdcsvax.UUCP (Darrell Long) Newsgroups: net.arch Subject: Re: A feature, not a bug Message-ID: <954@sdcsvax.UUCP> Date: Sat, 29-Jun-85 17:45:01 EDT Article-I.D.: sdcsvax.954 Posted: Sat Jun 29 17:45:01 1985 Date-Received: Tue, 2-Jul-85 05:33:53 EDT References: <1680@amdcad.UUCP> <420@mtxinu.UUCP> Reply-To: darrell@sdcsvax.UUCP (Darrell Long) Followup-To: net.jokes Distribution: net Organization: EECS Dept. U.C. San Diego Lines: 37 Keywords: 32-bit microprocessor Summary: WE-3200x chip Well, by looking at the code generated by the 3B-2/300 sitting beside me, I get some interesting results. Fully 10% of the code is made up of NOPs. Futher, NOPs are inserted in some very peculiar places. TSTW NOP BEB # a conditional branch! MOVW NOP PUSHW MOVW NOP MOVW CLRW NOP ADDW3 CLRW NOP MOVAW It should be noted that the insertions are by no means consistent, unless there is some strange alignment scheme (which would be a bug) that I haven't noticed. The above examples contain only mundane addressing modes, and no access to the PSW. -- Darrell Long Department of Electrical Engineering and Computer Science University of California, San Diego USENET: sdcsvax!darrell ARPA: darrell@sdcsvax