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From: ed@mtxinu.UUCP (Ed Gould)
Newsgroups: net.arch
Subject: Re: A feature, not a bug
Message-ID: <420@mtxinu.UUCP>
Date: Mon, 24-Jun-85 19:11:56 EDT
Article-I.D.: mtxinu.420
Posted: Mon Jun 24 19:11:56 1985
Date-Received: Sat, 29-Jun-85 02:40:37 EDT
References: <1680@amdcad.UUCP>
Reply-To: ed@mtxinu.UUCP (Ed Gould)
Organization: mt Xinu, Berkeley, CA
Lines: 32
Keywords: 32-bit microprocessor

In article <1680@amdcad.UUCP> bcase@amdcad.UUCP (Brian case) writes:
>I read the following in the "WE 32100 Microprocessor Information
>Manual" section 3.6.6 Stack and Miscellaneous Instructions:
>
>    If an instruction, other than a conditional transfer, reads
>    the PSW, the assembler m32as inserts a NOP before that
>    instruction.  This allows time for the PSW codes to settle
>    before the new instruction tries to access them.
>
>Ahem.  Allows the codes to settle?  Don't they need to settle before
>the conditional transfer can reliably take place?

That's not necessarily a bug at all.  It's probably the case (I don't
have any particulars on the WE chip) that the conditional transfer
instructions are interlocked so that they will always read the correct
codes (or perhaps they get the codes from an internal register other than
the PSW).  Other instructions rarely care about the condition codes
when accessing the PSW, so it's not unreasonable to make the programmer
(or in this case the assembler) be careful about timings like that.

I expect that the condition code-to-PSW loop was a long part of the
instruction cycle, so they decided to relax the "finish this one
before starting the next" requirements somewhat to keep things
going fast.

It's certainly not a feature, though.

-- 
Ed Gould		    mt Xinu, 2910 Seventh St., Berkeley, CA  94710  USA
{ucbvax,decvax}!mtxinu!ed   +1 415 644 0146

"A man of quality is not threatened by a woman of equality."