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From: john@frog.UUCP (John Woods)
Newsgroups: net.arch
Subject: Re: Novix Forth chip seen at Rochester Conference
Message-ID: <206@frog.UUCP>
Date: Mon, 24-Jun-85 13:40:05 EDT
Article-I.D.: frog.206
Posted: Mon Jun 24 13:40:05 1985
Date-Received: Thu, 27-Jun-85 08:28:00 EDT
References: <249@tekcbi.UUCP> <89300001@hpisla.UUCP>
Organization: Charles River Data Systems, Framingham MA
Lines: 36

> >a rate of approximately 10 Million Forth primitives per second (at a clock
> >rate of 8 MHz).
>   Amazing!
>   (a.k.a. Unbelievable!)
>   Unless I am missing something, even an *extremely* complex processor
>   could execute only 8 "Million Forth primitives per second (at a clock
>   rate of 8 MHz)."

I have the article on the Forth chip from Electronic Design, 21 March 1985
(DROOL DROOL DROOL!!!!!!!).  The key to how it works is in the following
statement, quoted from said article:

"The first chip to be released, the NC4000A, runs at a clock speed of 8MHz.
Each instruction executes in a single clock cycle, and performs as many as
five operations simultaneously -- for a chip speed of over 10 million
operations per second."

Most FORTH operations require most of the available chip operations, per
cycle, but several FORTH operations don't, and can be easily combined with
idiomatically subsequent FORTH operations for simultaneous execution, e.g.
operation pairs like @ +, OVER SWAP -, or the amazing DUP @ SWAP nn +
(an incrementing fetch, basically).

The chip (from the article) basically looks rather like a bitslice processor
which you get to write the microcode for (rather than it interpreting macro-
code).  The microcode is specially designed to be graceful for much of FORTH.
It also have 5 busses, two I/O busses, a "data stack" bus, a "return stack"
bus, and a "main memory" bus.  Implementing C on it looks like it might be
tricky, but it is clearly the ideal FORTH chip.

--
John Woods, Charles River Data Systems, Framingham MA, (617) 626-1101
...!decvax!frog!john, ...!mit-eddie!jfw, jfw%mit-ccc@MIT-XX.ARPA

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