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From: phil@amd.UUCP (Phil Ngai)
Newsgroups: net.micro.68k,net.micro.pc,net.arch
Subject: Re: x86/68x buses
Message-ID: <1500@amd.UUCP>
Date: Tue, 9-Jul-85 21:04:09 EDT
Article-I.D.: amd.1500
Posted: Tue Jul  9 21:04:09 1985
Date-Received: Thu, 11-Jul-85 04:56:49 EDT
References: <344@osu-eddie.UUCP> <600@intelca.UUCP> <2275@sun.uucp> <611@intelca.UUCP> <>
Reply-To: phil@amd.UUCP (Phil Ngai)
Organization: AMD, Santa Clara, CA
Lines: 22
Xref: watmath net.micro.68k:994 net.micro.pc:4487 net.arch:1534

>addresses).  Serious MMUs start to translate the address before AS
>anyway, so it actually helps to not have to latch the address, since
>as fast as the CPU can drive it, the MMU can start looking it up, rather

But you can't use the address until it is valid, which is the definition
of AS anyhow. You also seem to be confusing latch and register. A latch
such as the 74373 allows data to flow through it while enabled and
holds its output while disabled. A register such as the 74374 stores
its input on a clock edge. On the 8086, for example, you would use a 74373
and the address would be available at the time it was valid from the uP
plus the prop delay of the latch, which is comparable to the prop delay
of the address buffers you would need in a real system anyway. ALE
(address latch enable) is not the gating item it would be if a register
were used. If a 74374 were used, the address would be available a
prop delay after ALE went inactive, which in turn is some setup time
after address is valid.
-- 
 This is only my opinion and an unofficial one at that.

 Phil Ngai (408) 749-5720
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