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From: geoff@tolerant.UUCP (Geoffrey G. Peck)
Newsgroups: net.micro.16k
Subject: Re: Query about interrupt/trap handling
Message-ID: <114@tolerant.UUCP>
Date: Tue, 2-Jul-85 06:15:09 EDT
Article-I.D.: tolerant.114
Posted: Tue Jul  2 06:15:09 1985
Date-Received: Thu, 4-Jul-85 06:01:57 EDT
References: <1179@sjuvax.UUCP>
Distribution: net
Organization: Tolerant Systems, Inc.  San Jose, CA
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Interrupts and traps cause the processor to switch to supervisor state, at
which point exception (interrupt or trap) processing proceeds as per chapter
6 in the Series 32000 Instruction Set Reference Manual (June 1984).
Unfortunately, this rev of the manual doesn't contain much of the useful
information on memory management and protection that the older rev did.