Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site gatech.CSNET Path: utzoo!watmath!clyde!burl!ulysses!gatech!jeff From: jeff@gatech.CSNET (Jeff Lee) Newsgroups: net.arch Subject: Re: Re: RISC (really on multiplication d Message-ID: <582@gatech.CSNET> Date: Mon, 15-Jul-85 18:34:46 EDT Article-I.D.: gatech.582 Posted: Mon Jul 15 18:34:46 1985 Date-Received: Wed, 17-Jul-85 08:11:33 EDT References: <149@mips.UUCP> <36900009@ima.UUCP> <1777@amdahl.UUCP> Organization: School of ICS, Georgia Institute of Technology, Atlanta Lines: 34 > > > > Having a hardware multiplication instruction isn't as much of a win as > > you might think. On everybody's favorite chip, the 8088, a 16 x 16 > > multiply takes about 115 cycles, while shifts and adds are 2 and 3 cycles > > respectively. This means that for practically any constant multiplier > > you'll get faster code by constructing your multiply from shifts, adds, > > and substracts. Most engineers would disagree with this statement (I am NOT an engineer), that having hardware multiplication is not a big win. > Unless the multiplier is very wide and smart enough to do things like sum > partial products in parallel with each multiplication. This gives speed > you couldn't get with the above. However, it sure is not obvious what > the right thing to do is. I remember looking over the algorithms for the Cyber 170/750 hardware (or was it a 170/755; those old machines). The machines central clock was on order of 50ns. It performed wierd splits of the bits to produce the intermediate products and performed a heap of adding in parallel. The result was that the first stage of the pipeline (I think it was a 2 stage job) could accept a pair of operands (48-bit mantissa, 11-bit exponent, 1-bit sign) every 2 cycles. What sort of algorithm does Cray now use for his Cray-II machine? Does he get his multiplies done in a single clock cycle or are they still pipelined? A friend of mine (previously an electrical engineer, but turned computer science) took a class in hardware algorithms. It looked pretty interesting but also not your typical "seat-of-the-pants" type algorithms. Quite a bit of thought went into the magic.... -- Jeff Lee CSNet: Jeff @ GATech ARPA: Jeff%GATech.CSNet @ CSNet-Relay.ARPA uucp: ...!{akgua,allegra,hplabs,ihnp4,linus,seismo,ulysses}!gatech!jeff