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From: mat@amdahl.UUCP (Mike Taylor)
Newsgroups: net.arch
Subject: Re: Re: RISC (really on multiplication d
Message-ID: <1777@amdahl.UUCP>
Date: Thu, 11-Jul-85 23:12:26 EDT
Article-I.D.: amdahl.1777
Posted: Thu Jul 11 23:12:26 1985
Date-Received: Sat, 13-Jul-85 16:17:46 EDT
References: <149@mips.UUCP> <36900009@ima.UUCP>
Organization: Amdahl Corp, Sunnyvale CA
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> 
> Having a hardware multiplication instruction isn't as much of a win as
> you might think.  On everybody's favorite chip, the 8088, a 16 x 16
> multiply takes about 115 cycles, while shifts and adds are 2 and 3 cycles
> respectively.  This means that for practically any constant multiplier
> you'll get faster code by constructing your multiply from shifts, adds,
> and substracts.
> 
Unless the multiplier is very wide and smart enough to do things like sum
partial products in parallel with each multiplication.  This gives speed
you couldn't get with the above.  However, it sure is not obvious what
the right thing to do is.
-- 
Mike Taylor                        ...!{ihnp4,hplabs,amd,sun}!amdahl!mat

[ This may not reflect my opinion, let alone anyone else's.  ]