Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site ucbvax.ARPA Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxn!ihnp4!ucbvax!tcp-ip From: tcp-ip@ucbvax.ARPA Newsgroups: fa.tcp-ip Subject: Re: Plea for ICMP Timestamp support Message-ID: <8885@ucbvax.ARPA> Date: Mon, 8-Jul-85 22:54:40 EDT Article-I.D.: ucbvax.8885 Posted: Mon Jul 8 22:54:40 1985 Date-Received: Wed, 10-Jul-85 23:55:02 EDT Sender: daemon@ucbvax.ARPA Organization: University of California at Berkeley Lines: 29 From: Stephen CasnerDave, In our EPOS operating system, we use a different technique for the 60 Hz clock. Rather than adding the approximate fraction 2/3 to a fractional extension of the accumulator, we use a modulo-3 counter to add an extra 1 to the accumulator on 2 out of every 3 cycles. For the example of a millisecond clock, 17 is added on the first 2 out of 3 cycles and 16 is added on the third cycle. (In EPOS we actually keep a 48-bit clock of 40 microsecond ticks, but the principle is the same.) The advantage of this method is that it is exact rather than having an error of .000005 ms per 60 Hz tick or about 1 ms per hour. The number of instructions is about the same with either technique. Here is a code segment for the PDP11: DEC TRICYC ; Is this the third of three cycles? BPL 1$ ; No - just update time MOV #2,TRICYC ; Yes - reset the modulo-three counter ADD #INCTIM,UPTML ; Update time less 2/3 fraction to adjust BR 2$ ; for the two extra 1/3 fraction 1$: ADD #INCTIM+1,UPTML ; Update time including 1/3 fraction extra 2$: ADC UPTMM ; Carry the update out through 32 bits The BR 2$ can be eliminated by replicating code if that is practical. -- Steve -------