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Path: utzoo!linus!decvax!tektronix!hplabs!hp-pcd!orstcs!richardt
From: richardt@orstcs.UUCP (richardt)
Newsgroups: net.arch
Subject: Re: Re: 68000 "small model"
Message-ID: <12200003@orstcs.UUCP>
Date: Tue, 9-Jul-85 23:14:00 EDT
Article-I.D.: orstcs.12200003
Posted: Tue Jul  9 23:14:00 1985
Date-Received: Mon, 15-Jul-85 01:41:20 EDT
References: <2361@sun.UUCP>
Organization: Oregon State University - Corvallis, OR
Lines: 19
Nf-ID: #R:sun:-236100:orstcs:12200003:000:1099
Nf-From: orstcs!richardt    Jul  9 19:14:00 1985

While you're trying to simulate a segmented architecture, although
I can't see why anyone would want to, there is a very simple dodge:
designate one or more address registers as Data Register pointers,
and do the same for any other segments.  Then load the 'segment'
into the high word of the address register(s).  after doing this,
you can use indirect jumps (JMP.L (Ax)) to simulate a 64k code space,
after loading the offset into the low word of Ax;  you can address arrays
by loading the offset into the low word of the Data Segment Register (Ax)
and then use the standard array addressing modes, which is essentially
the same trick mentioned above;  and you can keep one Address register
as a dedicated segment register, and use array and offset modes to 
simulate the offset + segmant address.

Given that you can fake a segmented 68xxx, why bother?  It is usually
far easier to write relocatable code.  Unlike the Intel chips, its easy
with a 68xxx.  Another way of simulating a "small model" environment is
to program the MMU correctly.
						orstcs!richardt
"If I'm human, what are *YOU*?"