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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: risc, cisc, and microprogramming
Message-ID: <148@mips.UUCP>
Date: Sat, 29-Jun-85 19:18:08 EDT
Article-I.D.: mips.148
Posted: Sat Jun 29 19:18:08 1985
Date-Received: Tue, 2-Jul-85 05:29:21 EDT
References: <557@hou2b.UUCP> <1078@peora.UUCP> <334@spar.UUCP> <145@mips.UUCP> <350@spar.UUCP> <171@watmum.UUCP>
Organization: MIPS Computer Systems, Mountain View, CA
Lines: 38

> Chris Shaw    watmath!watmum!cdshaw  writes:
> Does not the average RISC type machine do a purge-pipe action upon
> receipt of a branch instruction, or is there something so incredibly obvious
> going on here that I am missing? ....
> Thus we have a bogus program with a 2-element pipe:
> start:	load  a
> 	store b
> start+2:add   c
> 	store d
> 	decr  e
> 	brnz  start+2:
> 	load  a		\  do these 2 if branch taken, else throw them away
> 	store b		/   ... (purge) and do the xor
> 	xor   a     ---> continue here because "load" & "store" were purged
> 			 ... when the branch was not taken

The idea in RISCs with branch-delay slots is to NEVER do purge-pipes,
except in interrupt-processing.  A typical RISC design like the above
would ALWAYS execute the 2 instructions following the branch,
so the pipe would never be purged.  A more likely code sequence would be:
  start:load  a
  start+1:store b
  start+2:add   c
  	decr  e
  	brnz  start+1:
  	store d
  	load  a	
  	xor   a 
[Note: the program is bogus, so it's hard to tell exactly what is going on,
but the 2nd example is much more in the spirit of the way RISCs work.
Worth reading are 2 excellent articles: Dave Patterson's Jan 85 CACM
article or John Hennessy's Dec 84 IEE Trans on Computers one.

-- 
-john mashey
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