Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: $Revision: 1.6.2.16 $; site ima.UUCP Path: utzoo!watmath!clyde!burl!ulysses!ucbvax!decvax!yale!ima!johnl From: johnl@ima.UUCP Newsgroups: net.arch Subject: Re: Re: RISC (really on multiplication d Message-ID: <36900009@ima.UUCP> Date: Sun, 7-Jul-85 15:27:00 EDT Article-I.D.: ima.36900009 Posted: Sun Jul 7 15:27:00 1985 Date-Received: Thu, 11-Jul-85 00:16:15 EDT References: <149@mips.UUCP> Lines: 14 Nf-ID: #R:mips:-14900:ima:36900009:000:647 Nf-From: ima!johnl Jul 7 15:27:00 1985 Having a hardware multiplication instruction isn't as much of a win as you might think. On everybody's favorite chip, the 8088, a 16 x 16 multiply takes about 115 cycles, while shifts and adds are 2 and 3 cycles respectively. This means that for practically any constant multiplier you'll get faster code by constructing your multiply from shifts, adds, and substracts. Even on other higher powered machines a multiply is still typically 10 times slower than an add or shift, so that it's still usually faster to do the addition chain for small multipliers such as the ones you usually run into when doing subscripting. John Levine, ima!johnl