Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/17/84 chuqui version 1.7 9/23/84; site daisy.UUCP Path: utzoo!watmath!clyde!cbosgd!ihnp4!mhuxn!mhuxj!mhuxr!ulysses!allegra!bellcore!decvax!ittvax!dcdwest!sdcsvax!sdcrdcf!hplabs!nsc!daisy!david From: david@daisy.UUCP (David Schachter) Newsgroups: net.micro,net.micro.pc Subject: Re: Standard, What standard??? Message-ID: <77@daisy.UUCP> Date: Wed, 27-Feb-85 22:49:19 EST Article-I.D.: daisy.77 Posted: Wed Feb 27 22:49:19 1985 Date-Received: Mon, 4-Mar-85 04:58:03 EST References: <143@idmi-cc.UUCP> <810@sjuvax.UUCP> <56@daisy.UUCP> <287@cmu-cs-k.ARPA> Reply-To: david@daisy.UUCP (David Schachter) Organization: Daisy Systems Corp., Mountain View, Ca Lines: 28 Xref: watmath net.micro:9575 net.micro.pc:3430 Summary: Mr. Nowatzyk of Carnegie Mellon states that 64K segmentation limits have caused him problems in using 80286 software on our workstations. If he is running very large designs through our older software, this can happen. This has been corrected in newer releases in those places where it has caused problems. (When we designed the software, we designed it with what we thought were generous safety margins. Our customers promptly used the increased efficiency of computer aided engineering to do much larger designs than before! Parkinson's law strikes again.) All of the newer software, particularly in the physical layout tools and in the hardware accelerator realm have taken advantage of what we learned in doing the older software. (That's what I meant in my earlier posting when I used the term "experience.") We learned, in short, how to design our code to run in the method intended by the designers of the CPU. If you want to get maximum performance on a CPU you didn't design, this is always a requirement, be it a NS32000, an MC68000, an 80286, or a PDP-8. In our experience writing CAE software, in the rare cases where 64K segmentation is a problem, it usually means that we don't know what we are doing yet. There is almost always a better algorithm that we haven't discovered yet, one which uses smaller data structures >faster<. Large address spaces are convenient. They are not essential. Moreover, their convenience can rob you of the incentive to get maximum performance. The Intel architecture is a dark cloud with a silver lining: the need to keep within the small address space frequently causes us to find solutions that are smaller and faster, helping us meet our performance goals.