Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: notesfiles Path: utzoo!watmath!clyde!burl!ulysses!allegra!bellcore!decvax!ittvax!dcdwest!sdcsvax!sdcrdcf!hplabs!hp-pcd!hp-dcde!perry From: perry@hp-dcde.UUCP (perry) Newsgroups: net.arch Subject: Re: Re: Cube designs vs. x,y,z bus Message-ID: <1500003@hp-dcde.UUCP> Date: Sun, 17-Feb-85 20:31:00 EST Article-I.D.: hp-dcde.1500003 Posted: Sun Feb 17 20:31:00 1985 Date-Received: Mon, 4-Mar-85 08:14:09 EST References: <268@oliveb.UUCP> Organization: Hewlett-Packard - Fort Collins, CO Lines: 41 Nf-ID: #R:oliveb:-26800:hp-dcde:1500003:000:2104 Nf-From: hp-dcde!perry Feb 27 17:31:00 1985 > /***** hp-dcde:net.arch / oliveb!jerry / 5:49 pm Feb 21, 1985*/ > > If your thinking that 1M processors is unreasonable then think again. > Depending on the memory in each processor 1 to several processors could > be placed on a single chip. As the only IO required is for the > hyper-channel connections the number of pin-outs is minimal. As a 1M > array would, by definition, get volume pricing each chip might cost > only a dollar or so. > > If each processor had 16K bytes of memory, a 1M array would result in a > computer with 16,000 Meg (16 gigabytes) of ram. If the entire wafer of > silicon was used then the wasted area used for cutting the chips apart > could be eliminated. It would be possible to get many processors on on > wafer with only 30 or so external connections required. > > Jerry Aguirre @ Olivetti ATC > {hplabs|fortune|idi|ihnp4|tolerant|allegra|tymix}!oliveb!jerry > /* ---------- */ Although it makes sense to put entire chipsets on the same wafer, you're going to run up against several problems: 1) Heat dissipation. I looked up the dissipation for Motorola's 68000 CPU and their 256Kx1 RAM. The 68000 dissipates 1.5W, and the 256Kx1 dissipates 350mW. For the configuration you suggest, each processing element will require 1.5 + 2*.350 = 2.2W. This does not include connecting circuitry, such as hyperchannel, DMA controllers, etc. Although I don't know the maximum amount of heat that a wafer can dissipate, it would appear that even 4 CPU/RAM's would be pushing it. 2) Yield. As circuit complexity increases, yield decreases. Having all those circuits be correct simultaneously may be a statistical impossibility. 3) Cost. If (1) requires different (more expensive) cooling technology, and (2) makes yields even lower, the volume price would still be higher. CPU chips still cost big bucks all by themselves. Adding more to the complexity may result in a commercially (not to mention technically) infeasible design. Perry Scott, HP-FSD ...{allegra|ihnp4|decvax|ucbvax}!hplabs!hpfcla!perry-s