Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/18/84; site fortune.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!ihnp4!fortune!yamauchi
From: yamauchi@fortune.UUCP (Alan Yamauchi)
Newsgroups: net.arch
Subject: Re: Multi-valued logic
Message-ID: <5067@fortune.UUCP>
Date: Fri, 1-Mar-85 13:01:35 EST
Article-I.D.: fortune.5067
Posted: Fri Mar  1 13:01:35 1985
Date-Received: Sat, 2-Mar-85 04:43:46 EST
References: <1384@ut-ngp.UUCP>
Reply-To: yamauchi@fortune.UUCP (Alan yamauchi)
Organization: Fortune Systems, Redwood City, CA
Lines: 28
Keywords: Voltage multiplexed pins

In article <1384@ut-ngp.UUCP> vomlehn@ut-ngp.UUCP (vomlehn) writes:
>
>One application of multi-valued logic which I have never heard of is voltage-
>multiplexing pins. . . . Some chip makers time-multiplexed pins, so that the
>same set of pins may have address information during one time interval and
>data information during the next.  If the pins were voltage-multiplexed
>a given pin would only contain data, but it would contain the data for two
>logical data lines. 

Voltage multiplexed pins are already being implemented at some of the semi-
conductor houses now, although not quite in the manner you suggested.  This is
done strictly for in house test purposes and mostly with the more complex
parts such as uComputers and uProcessors.  Applying voltages > 7V to certain 
pins on these parts allows the testers to dump either internal masked ROM
or uCode.  I'm not sure of exact voltage levels necessary to change the
functionality of pins, but some other semi houses use an alternate method
of dumping ROM or uCode, such as forcing certain opcodes in special sequences.
Of course most of this in not common knowledge unless you've either worked
in or are working in a semiconductor house.  The technology to do what you 
suggest certainly exists, but to do it commercially in the bi-level logic
world now would be quite costly.

                        \   /
      Alan Yamauchi       *
                        \___/
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