Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site decwrl.UUCP Path: utzoo!watmath!clyde!burl!ulysses!allegra!bellcore!decvax!decwrl!dec-rhea!dec-jaws!jackson From: jackson@jaws.DEC (I'm all right jack, keep your hands off my stack) Newsgroups: net.arch Subject: Help on choosing a bus Message-ID: <999@decwrl.UUCP> Date: Thu, 7-Mar-85 10:09:03 EST Article-I.D.: decwrl.999 Posted: Thu Mar 7 10:09:03 1985 Date-Received: Sat, 9-Mar-85 11:28:52 EST Sender: daemon@decwrl.UUCP Organization: DEC Engineering Network Lines: 29 I am in the process of evaluating other bus structures (other than the ones that we use within DEC) I am currently evaluating the Nu bus (Texas Instruments), VMEbus (Motorola/signetics) and Multibus II (Intel) Questions have come up within our group about design tools for designing options for these busses. This would include standard layout tools which have board shapes, etc already defined, and simulation tools for the chips that are available from the bus vendor. What is available out there? (either standalone, VMS based, or ULTRIX based, I can't get other versions) Also, if people who have designed options for these busses would provide some information on why they chose a specific bus, how much resources (time, people, compute power, and parts) it took to do the design, and overall 'completeness' of the specifications would be greatly appreciated. responses to me directly will be summarized in net.arch bill jackson Digital Equipment Corp. Hudson Mass (617)568-4083 ARPA: Jackson%JAWS.DEC@decwrl.arpa USENET: {allegra|decvax|ihnp4|ucbvax}!decwrl!dec-rhea!dec-jaws!jackson