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From: brooks@lll-crg.ARPA (Eugene D. Brooks III)
Newsgroups: net.arch
Subject: Re: Re: Cube designs vs. x,y,z bus.  What is it?
Message-ID: <437@lll-crg.ARPA>
Date: Tue, 5-Mar-85 23:46:19 EST
Article-I.D.: lll-crg.437
Posted: Tue Mar  5 23:46:19 1985
Date-Received: Sat, 9-Mar-85 19:27:43 EST
References: <48@pbear.UUCP> <268@oliveb.UUCP> <171@redwood.UUCP> <304@oliveb.UUCP>
Organization: Lawrence Livermore Labs, CRG group
Lines: 30

If you are going to explain what a hypercube is you should get the topology
correct.  This topology is very important.

A hypercube is composed of { 2 sup n } processors.  n is called the order of
the hypercube.  A hypercube of order n+1 is constructed by taking two of
order n and placing them side by side connecting pairs of processors like so.

order 0		p0		/* Bet you didn't that there are a lot of
				hypercubes out there already *?

order 1		p0---p1

order 2		p0---p1
		|    |
		|    |
		p2---p3

order 3		p0-----p1
		| \    | \
		|  p4--|--p5
		|  |   |  |
		p2-----p3 |
		  \|     \|
		   p6-----p7

By inspection of the processor numbers you can discover the master plan.
The processors run from 0 to N-1 where N is some power of 2.  Each processor
is connected to all of the processors whose index differs in one and only
bit.  The position of the differing bit is the port which the two processors
are connected with.