Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site bmcg.UUCP Path: utzoo!linus!philabs!cmcl2!seismo!hao!hplabs!sdcrdcf!trwrb!trwrba!cepu!bmcg!mikel From: mikel@bmcg.UUCP (Mike Lesher) Newsgroups: net.micro.16k Subject: Re: Questions about Scaled Index addressing mode Message-ID: <1630@bmcg.UUCP> Date: Sat, 9-Mar-85 16:02:44 EST Article-I.D.: bmcg.1630 Posted: Sat Mar 9 16:02:44 1985 Date-Received: Tue, 12-Mar-85 09:32:03 EST Reply-To: mikel@bmcg.UUCP (Mike Lesher) Distribution: net Organization: Burroughs Corporation, San Diego Lines: 31 [Row, row, row your bits, gently down the stream...] In article <> dcs@gitpyr.UUCP (David Sowell) writes: >------ > >I have some questions about the NS32032's addressing modes: > > What does the Scaled Index addressing option do when applied > to a Register addressing mode? In other words, what does > something like "MOVW R1[R3:B],R0" do? > > What results from doing something like "ADDR R1,R0"? > >I do not have a machine to try these out on, otherwise I would. I am >designing a high level assembly language for the 320xx family and I need >to know what is meant by the above constructions. > > >David C Sowell >Georgia Insitute of Technology, Atlanta Georgia, 30332 >...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs I have tried these instruction on our system an found: MOVW R1[R3:B],R0 = MOVW @(R1+R2), R0 ADDR R1,R0 = MOVD R1, R0 I hope this answers your questions. Mike Lesher Burroughs ASG, San Diego, CA. (..!bmcg!mikel)