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From: info-vlsi@ucbvax.ARPA
Newsgroups: fa.info-vlsi
Subject: question on CMOS processing
Message-ID: <5395@ucbvax.ARPA>
Date: Sat, 9-Mar-85 17:24:10 EST
Article-I.D.: ucbvax.5395
Posted: Sat Mar  9 17:24:10 1985
Date-Received: Sun, 10-Mar-85 07:40:35 EST
Sender: daemon@ucbvax.ARPA
Organization: University of California at Berkeley
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From: 


We have been participants on an MPC. The technology is 5 micron CMOS (AMI).
On testing we find that all outputs show levels in the range of 2-3 Volts,
using a supply of 5 Volts. We have measured both pull-up and pull-down
transistors in the pad driver to be ON. This also explains the rather high
power consumption. Now, other chips on the MPC have had working pad-drivers
so we must conclude processing has been O.K.
  Can anyone explain how both pull-up and pull-down transistors can be
switched on? And also what we should look for when we get access to a probe-
station? I must also mention that we have used the 5 micron standard cell
library from AMI.
  Please answer directly to me, as I have not received any mail yet from the
INFO-VLSI mailing list.
				      Best Regards, Harald Haugan

Harald Haugan                   Usenet: ucbvax!decvax!mcvax!cernvax!harald
CERN, Division DD               ARPA: no direct connection, but
1211 Geneve 23                  bassen@oslo-vax   will eventually get here.
Switzerland