Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site sdcrdcf.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!ihnp4!houxm!whuxl!whuxlm!akgua!sdcsvax!sdcrdcf!doon From: doon@sdcrdcf.UUCP (Harry W. Reed) Newsgroups: net.micro.16k Subject: Re: Questions about Scaled Index addressing mode Message-ID: <1821@sdcrdcf.UUCP> Date: Fri, 8-Mar-85 13:09:19 EST Article-I.D.: sdcrdcf.1821 Posted: Fri Mar 8 13:09:19 1985 Date-Received: Sun, 10-Mar-85 07:36:01 EST References: <200@gitpyr.UUCP> Reply-To: doon@sdcrdcf.UUCP (Harry W. Reed) Distribution: net Organization: System Development Corp. R+D, Santa Monica Lines: 68 Summary: In article <200@gitpyr.UUCP> dcs@gitpyr.UUCP (David Sowell) writes: >------ > >I have some questions about the NS32032's addressing modes: > > What does the Scaled Index addressing option do when applied > to a Register addressing mode? In other words, what does > something like "MOVW R1[R3:B],R0" do? > > What results from doing something like "ADDR R1,R0"? > >I do not have a machine to try these out on, otherwise I would. I am >designing a high level assembly language for the 320xx family and I need >to know what is meant by the above constructions. > >In the documentation I have (see below) nothing is said about the legality >of these constructions. It does say that Scaled Index may not be applied >to the Immediate addressing mode or another Scaled Index addressing mode. >I understand how Scaled Index works for the other combinations. I am >surprised that if the above constructions are meaningless, it is not stated >so in the documentation. > >Admittedly, most of my documentation is old. More current manuals may >address this issue (sorry about the pun...). I have these documents: > > NS16000 Microprocessor Family Reprint of Technical Articles (1980) > > NS16000 Programmers's Reference Manual > (Feb. 1982) > > NS32032-6,NS32032-10 High-Performance Microprocessors > (Preliminary Data Sheet, Feb. 1984) > > NS16032 High-Performance Microprocessor > (Preliminary Data Sheet, Apr. 1982) > > NS16201 Timing Control Unit (TCU) > (Preliminary Data Sheet, June 7, 1981, Rev. H) > > NS16202 Interrupt Control Unit > (Preliminary Data Sheet, Oct. 1982) > > NS16082 Memory Management Unit (MMU) > (Preliminary Data Sheet, Mar, 1982) > > > Thanks, > David Sowell > > >David C Sowell >Georgia Insitute of Technology, Atlanta Georgia, 30332 >...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs David: I, like you, am developing software for the 32000 without any hardware to try things on. In my case I'm writing a cross-assembler for the 32000 family that will be used in conjunction with a port of Pcc. I to have wondered about the results of such things as ... r0[r1:q]. I think (and hope) the 32000's microcode realizes that this is rather meaningless. It is indeed odd that this form of scaled indexed addressing is allowed. I'm glad to know that i'm not alone in not knowing what that type of construct does. Cordially, Harry Reed