Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!henry From: henry@utzoo.UUCP (Henry Spencer) Newsgroups: net.rumor,net.unix-wizards Subject: Microvax 2 chip set Message-ID: <4880@utzoo.UUCP> Date: Mon, 7-Jan-85 20:14:17 EST Article-I.D.: utzoo.4880 Posted: Mon Jan 7 20:14:17 1985 Date-Received: Mon, 7-Jan-85 20:14:17 EST Organization: U of Toronto Zoology Lines: 31 The following is some interesting information, from a source I will not name (and don't bother asking for more info, you're getting all I've got), about a forthcoming chip set from DEC, the "Microvax 2 [II?]" chips. The cpu chip, which implements the Microvax instruction set (i.e. VAX minus a few of the sillier things) and has memory management on-chip, is the 78032. (This is pronounced "seven-eighty-thirty-two" for some reason, not "seventy-eight-oh-thirty-two".) The floating-point chip, a tightly-coupled coprocessor, is the 78132. There is a DMA controller (78532), a DRAM controller (78584), and a vectored-interrupt chip (78516) to match. In-Circuit-Emulation goodies will follow. The chips are bug-free (or roughly so) in the lab, to the extent that both VMS and Ultrix are already running on them. Benchmarking is being done, so it can be safely assumed that they are running at near-final clock speeds as well. "What about the benchmarking", you ask... The story I have is that they are consistently faster than the 750, although not consistently up to a 780. Some instructions are actually a bit faster than on a 780, but the overall speed is somewhat lower. They will probably appear first in a system-level product, which will be a Q-bus machine with a private (i.e. fast) cpu-to-memory bus. They will then work their way down to board-level and chip-level products. "When", you ask... My source claims that announcement timing is the subject of hot debate, but the word is "months". -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,linus,decvax}!utzoo!henry