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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: time for a RISCy bus
Message-ID: <4940@utzoo.UUCP>
Date: Wed, 16-Jan-85 17:29:40 EST
Article-I.D.: utzoo.4940
Posted: Wed Jan 16 17:29:40 1985
Date-Received: Wed, 16-Jan-85 17:29:40 EST
Organization: U of Toronto Zoology
Lines: 26

(Sorry about the title, I couldn't resist.)

Of late, we have seen announcements of the VME bus, the Multibus II,
the IEEE whatever-it's-called-this-week bus, the TI Nu-bus, and maybe
one or two that I've missed.  While all these bus schemes do have
interesting characteristics, there is one disturbing problem that they
all share:

Every last one of them is appallingly complex.

(Well, maybe I'm slandering the Nu-bus a little bit, but not the others.)

It has reached the stage where a recent review article on one of them
(the VME bus, I think) said, essentially, "nobody's implemented the
XYZ sub-bus yet, because company Q hasn't yet shipped the new VLSI IC
needed to run it".  Ye Gods!  Note that this wasn't even a whole bus,
just one specialized piece of it.

It is high time somebody did for bus structures what the RISC has done
for machine architecture:  provided a simple, high-performance alternative
to the convoluted, baroque "mainstream" approach.  Preferably before
we need a forklift to carry a bus spec -- a day that is fast approaching.
Anybody got any bright ideas?
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,linus,decvax}!utzoo!henry