Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!watmath!clyde!bonnie!akgua!sdcsvax!dcdwest!ittvax!decvax!cca!ima!inmet!stern From: stern@inmet.UUCP Newsgroups: net.arch Subject: Re: Re: RISC vs VAX Message-ID: <1839@inmet.UUCP> Date: Thu, 29-Nov-84 01:08:27 EST Article-I.D.: inmet.1839 Posted: Thu Nov 29 01:08:27 1984 Date-Received: Sat, 1-Dec-84 19:33:51 EST Lines: 33 Nf-ID: #R:utzoo:-465700:inmet:2500012:000:1922 Nf-From: inmet!stern Nov 27 10:51:00 1984 [got the asbestos jumpsuit on?] (1) I said that RISCs are not suited for floating point/matrix multiplication because: (a) attaching a floating point coprocessor to a RISC perverts the very idea of a reduced instruction set; and (b) the original question asked if a RISC could be produced in the same class as a VAX. No RISC can perform every function of a 780 faster than a 780 because there are tradeoffs made when you give up instruction set complexity for speed. Usually floating point stuff is the first to go -- except when you make a purely floating-point processor, in which case everything has been given up. You can't have your floating point cake and eat it too. (2) Yes, an ACIA and a VAX have different cycle times. So do a washing machine and an ECL flip-flop. But if you build a fancy interface to the ECL flip-flops, the washing machine still won't be able to talk to them. Having a nice DZ-11 multiplexor on a VAx is great -- it provides intelligent communications processing, so the VAX doesn't burn cycles doing low-level ACIA handshaking. Now how could a RISC talk to a DZ? Letting them share a memory space might be the best thing, but gee, then you might need another processor to arbitrate memory accesses, and then it starts to look like plugging a RISC into a VAX again. My point is that if you want a RISC to do i/o *without another processor* then you have to add instructions/wait states/more complexity to get something with a 50-nanosecond cycle time to talk to a device with a 1-microsecond cycle time. Comparing a RISC to a VAX in terms of performance, when the RISC has two or three half- or quarter-VAXen doing its i/o, is cheating. Hey, my Toyota can outrace the space shuttle when you strap two solid rocket boosters to it. --Hal Stern {ihnp4, harpo, esquire, ima}!inmet!stern