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Path: utzoo!watmath!clyde!bonnie!akgua!sdcsvax!dcdwest!ittvax!decvax!cca!ima!ISM780B!paul
From: paul@ISM780B.UUCP
Newsgroups: net.arch
Subject: Re: cache designs
Message-ID: <125@ISM780B.UUCP>
Date: Thu, 29-Nov-84 00:43:44 EST
Article-I.D.: ISM780B.125
Posted: Thu Nov 29 00:43:44 1984
Date-Received: Sat, 1-Dec-84 19:33:05 EST
Lines: 41
Nf-ID: #R:dartvax:-257100:ISM780B:23300001:000:1975
Nf-From: ISM780B!paul    Nov 22 12:38:00 1984

> Now suppose we had a cache that was much more under a programmer's control.
> To be concrete, suppose we have a cache of say, 32 elements each containing
> 32 words.  And suppose our processor has a load cache instruction with
> syntax:

>     load cache  

> When this instruction was executed, the instruction execution processor
> would quickly tell the cache processor to pick up some data from memory.
> Now, while the cache processor is picking up the data, the instruction
> processor continues executing instructions which are already in cache.

You may have just re-invented registers, and part of the rational
for a RISC machine with tons of registers, and memory addressing restricted
to explicit load and store instructions.  Current supercomputers tend to
be built this way already.

> ...For example, at
> the beginning of each 32 word chunk of code, the programmer might load
> the next 32 word chunk of code into cache, a chunk of code that might
> be branched to, and a few memory locations that would soon be accessed.

Automatic prefetching of instructions is a common way of speeding
up a cpu.  The bigger the machine, the bigger the prefetch cache.
It is sometimes suggested that branch instructions should allow
the programmer (or compiler) to indicate which way the branch is
most likely to go; this would make "automatic" instruction prefetching
"virtually" equivalent to explicit instruction cache control.

Paul Perkins    --      INTERACTIVE Systems
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