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From: dgreen@ucla-cs.UUCP
Newsgroups: net.arch
Subject: Re: cache designs
Message-ID: <2405@ucla-cs.ARPA>
Date: Mon, 26-Nov-84 17:58:58 EST
Article-I.D.: ucla-cs.2405
Posted: Mon Nov 26 17:58:58 1984
Date-Received: Thu, 29-Nov-84 05:33:13 EST
References: <2571@dartvax.UUCP> <27800035@uiucdcs.UUCP>
Reply-To: dgreen@ucla-cs.UUCP (Dan Greening)
Organization: UCLA Computer Science Department
Lines: 31
Summary: 

Regarding predictive hardware caches, and indeed almost everything else you
wanted to know about performance of hardware caches, please refer to the
following survey article:

Alan J. Smith, "Cache Memories," in ACM Computing Surveys, vol. 14, number 3,
September 1982.

He outlines three cache prefetch algorithms:

1. Always prefetch.  Whenever you access memory block x, prefetch memory block
   x+1.
2. Prefetch on misses.  Whenever you attempt to access memory block x, and x is
   missing from the cache, prefetch memory block x+1.
3. Tagged prefetch.  "We associate with each line a single bit called the tag,
   which is set to one whenever the line is accessed by a program.  It is
   initially zero and is reset to zero when the line is removed from the cache.
   Any line brought to the cache by a prefetch operation retains its tag of
   zero.  When a tag changes from 0 to 1 (i.e., when the line is referenced for
   the first time after prefetching or is demand-fetched), a prefetch is
   initiated for the next sequential line.  The idea is very similar to
   prefetching on misses only, except that miss which did not occur because the
   line was prefetched (i.e., had there not been a prefetch, there would have
   been a miss to this line) also initiates a prefetch."

"... always prefetching cut the miss ratio by 50 to 90 percent ... and tagged
prefetch was almost equally effective.  Prefetching only on misses was less
than half as good ..."

(all quotes from Smith)

Dan Greening, Computer Science Department UCLA.