Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site amdcad.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxj!ihnp4!amdcad!phil From: phil@amdcad.UUCP (Phil Ngai) Newsgroups: net.arch Subject: Re: Re: RISC vs VAX Message-ID: <328@amdcad.UUCP> Date: Sat, 1-Dec-84 04:06:59 EST Article-I.D.: amdcad.328 Posted: Sat Dec 1 04:06:59 1984 Date-Received: Sun, 2-Dec-84 04:14:17 EST References: <1839@inmet.UUCP> Organization: AMDCAD, Sunnyvale, CA Lines: 16 > --Hal Stern > is that if you want a RISC to do i/o *without another processor* then > you have to add instructions/wait states/more complexity to get something > with a 50-nanosecond cycle time to talk to a device with a 1-microsecond > cycle time. Give me a break. Haven't you ever heard of wait states, interrupts, or DMA? Did you know that an 8 MHz 8086 can't talk to a 4 MHz 8530 without wait states? No, I didn't need half a VAX to interface the 8086 to the 8530. What is your problem anyway? -- I'm not a programmer, I'm a hardware type. Phil Ngai (408) 749-5790 UUCP: {ucbvax,decwrl,ihnp4,allegra}!amdcad!phil ARPA: amdcad!phil@decwrl.ARPA