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Path: utzoo!watmath!wateng!padpowell
From: padpowell@wateng.UUCP (PAD Powell)
Newsgroups: net.arch
Subject: Re: Re: RISC vs VAX
Message-ID: <1711@wateng.UUCP>
Date: Sun, 2-Dec-84 08:49:18 EST
Article-I.D.: wateng.1711
Posted: Sun Dec  2 08:49:18 1984
Date-Received: Tue, 4-Dec-84 05:20:36 EST
References: <1839@inmet.UUCP>, <270@rlgvax.UUCP>
Organization: U of Waterloo, Ontario
Lines: 11

> (1) I said that RISCs are not suited for floating point/matrix multiplication
>     because: (a) attaching a floating point coprocessor to a RISC perverts
>     the very idea of a reduced instruction set; and (b) the original question

So what?  The concept of a RISC also violated the CISC aesthetic ideals.
If you want to argue that the addition of specialized hardware to perform
an algorithm unsuited for Von Neuman based architectures is an unsuitable
addition to a RISC architecture,  present proof, either mathematical,
or physical (i.e.- run an experiment), but please do not appeal to "good taste."

Patrick ("I'd put an FPA on my carburetor if it gave me better milage") Powell