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From: thomson@uthub.UUCP (Brian Thomson)
Newsgroups: net.lang.c
Subject: Re: ANSII C, optimization, and "hardware registers"
Message-ID: <185@uthub.UUCP>
Date: Fri, 19-Oct-84 11:39:19 EDT
Article-I.D.: uthub.185
Posted: Fri Oct 19 11:39:19 1984
Date-Received: Fri, 19-Oct-84 12:30:30 EDT
References: <1538@wateng.UUCP>, <2747@ucbcad.UUCP>
Organization: CSRG, University of Toronto
Lines: 37

The 'volatile' keyword will tell an (optimizing) compiler that a
location can change value asynchronously, but sometimes that isn't
enough.
Another common idiosyncrasy of hardware is that it is read-only
or write-only, or can only be accessed using byte or halfword or
fullword accesses.
I believe the Ritchie PDP-11 compiler would compile
		a = b + c;
into
		mov	b,a
		add	c,a
in appropriate circumstances; this clearly will fail if 'a' refers to
a write-only register.
The second situation is exemplified by registers in nexus space
on a Vax (forgive me if you don't know what this means), which
may only be accessed as longwords, and by Unibus registers which
may only be accessed as bytes or halfwords.
A favourite improvement made by /lib/c2 when compiling
		short a;
		...
		if (a&1) ...
is to replace the straightforward
		bitw	$2,_a
		jeql	L1
by
		jlbc	_a,L1
(Jump if Lower Bit Clear, that means) which is fine except that
the first sequence references _a as a halfword while the second
does a longword reference.

( the undocumented "-i" flag to vax /lib/c2 disables
  these optimizations that alter reference size, and doesn't have
  anything to do with memory volatility as suggested by an earlier
  article )
-- 
		    Brian Thomson,	    CSRI Univ. of Toronto
		    {linus,ihnp4,uw-beaver,floyd,utzoo}!utcsrgv!uthub!thomson