Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/17/84; site opus.UUCP Path: utzoo!linus!philabs!cmcl2!seismo!hao!cires!nbires!opus!rcd From: rcd@opus.UUCP (Dick Dunn) Newsgroups: net.arch Subject: byte alignment and interleaving Message-ID: <883@opus.UUCP> Date: Thu, 11-Oct-84 19:42:39 EDT Article-I.D.: opus.883 Posted: Thu Oct 11 19:42:39 1984 Date-Received: Sat, 13-Oct-84 03:59:16 EDT References: <426@ima.UUCP> Organization: NBI,Inc, Boulder CO Lines: 25 Somewhat of a side issue on byte alignment: > I suppose it would be possible to have fiendishly clever memory designs > where adjacent words were always in different memory banks so you could > cycle both at the same time. Sounds pretty awful, though, since you have > to determine for each memory reference how many memories to cycle and how > to splice the parts together. As far as I can tell, it's never been > seriously proposed for implementation, except perhaps incidentally in very > large cached architectures such as the IBM 308X. There's nothing "fiendishly clever" required. Just decode the address differently--use the lower bits as bank select instead of the higher bits. "Cycling" the memories isn't a problem. Splicing the parts is, but that problem happens with or without the interleaving. This scheme of addressing was used on the old CDC 6x00 series machines. It wasn't for the purpose of avoiding alignment problems, though--since the machines were word-addressable. It did serve to speed up programs which accessed sequential locations in main memory, and it made transfers between main memory and a backing bulk core storage FAST: 600 Mbits / sec, which is substantial considering the main memory had a 1 us cycle and the bulk core a 3.2 us cycle. -- Dick Dunn {hao,ucbvax,allegra}!nbires!rcd (303)444-5710 x3086 ...Relax...don't worry...have a homebrew.