Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83 based; site houxl.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxj!houxm!houxl!ksg From: ksg@houxl.UUCP (K.GRANT) Newsgroups: net.arch Subject: Arbitrary byte alignment Message-ID: <470@houxl.UUCP> Date: Wed, 3-Oct-84 11:11:14 EDT Article-I.D.: houxl.470 Posted: Wed Oct 3 11:11:14 1984 Date-Received: Thu, 4-Oct-84 02:39:01 EDT Organization: AT&T Bell Labs, Holmdel NJ Lines: 17 I'm interested in the byte alignment problem which exists in 32 bit machines. If a processor is given an address for a 32 bit operand (hereafter called a word) which is not aligned on a word boundary it can either: 1) fault 2) fetch the word in two accesses. (Are there memories which support arbitrarily aligned accesses to bytes, two byte quantities, and four byte quantities? If not, why not?) Do most processors support the first or second option? If a processor chooses the second option, how does it handle memory faults between accesses? How does it support restartability of that instruction? What other problems have I omitted? Does the logic design become unbearable? Thanks, houxl!ksg