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From: guy@rlgvax.UUCP (Guy Harris)
Newsgroups: net.arch
Subject: Re: byte alignment and interleaving
Message-ID: <193@rlgvax.UUCP>
Date: Sat, 13-Oct-84 01:28:07 EDT
Article-I.D.: rlgvax.193
Posted: Sat Oct 13 01:28:07 1984
Date-Received: Sun, 14-Oct-84 04:48:47 EDT
References: <426@ima.UUCP> <883@opus.UUCP>
Organization: CCI Office Systems Group, Reston, VA
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> > I suppose it would be possible to have fiendishly clever memory designs
> > where adjacent words were always in different memory banks so you could
> > cycle both at the same time.  Sounds pretty awful, though, since you have
> > to determine for each memory reference how many memories to cycle and how
> > to splice the parts together.  As far as I can tell, it's never been
> > seriously proposed for implementation, except perhaps incidentally in very
> > large cached architectures such as the IBM 308X.
> 
> There's nothing "fiendishly clever" required.  Just decode the address
> differently--use the lower bits as bank select instead of the higher
> bits. ... This scheme of addressing was used on the old CDC 6x00 series
> machines. ... It did serve to speed up programs which accessed sequential
> locations in main memory...

As Dick Dunn points out *via* his title, this is actually the standard
technique known as "memory interleaving", used on a number of machines.
Most machines with interleaved memory don't cycle the banks at the same time,
as all banks are on a common memory bus; however, you don't have to wait for
the bank with word N to recover from the fetch before fetching the next word,
you merely need wait till the word is fetched.  (A principle useful elsewhere
in life, at least if you have a dirty enough mind.)

	Guy Harris
	{seismo,ihnp4,allegra}!rlgvax!guy