Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site decwrl.UUCP Path: utzoo!watmath!clyde!burl!hou3c!hocda!houxm!ihnp4!zehntel!dual!decwrl!dec-rhea!dec-dosadi!binder From: binder@dosadi.DEC (The Stainless Steel Rat) Newsgroups: net.micro,net.misc Subject: net.digital - re: Pal and tri-state gate outputs Message-ID: <3659@decwrl.UUCP> Date: Mon, 17-Sep-84 13:49:36 EDT Article-I.D.: decwrl.3659 Posted: Mon Sep 17 13:49:36 1984 Date-Received: Tue, 25-Sep-84 05:57:23 EDT Sender: daemon@decwrl.UUCP Organization: DEC Engineering Network Lines: 22 > Anyway, does anyone know if tri-state outputs on PALs are guaranteed > not to glitch entering/leaving tri-state? > Ken Shoemaker, Intel, Santa Clara, Ca. I asked Bill Collins of National Semi to investigate the question of glitches on PLA outputs during enable transitions, and I have Bill's permission to quote his answer, which was given after he spent some time both looking at the circuitry and at the bench. National's PALs do NOT glitch when the tri-state enable is changed, either to ENable or to DISable. They simply change from the high impedance state to the asserted logic state when enabled, or from assertion to high impedance when disabled. This statement is not guaranteed to be true for MMI or AMD or anyone else's PALs... Cheers, Dick Binder (The Stainless Steel Rat) UUCP: { decvax, allegra, ucbvax... }!decwrl!dec-rhea!dec-dosadi!binder ARPA: binder%dosadi.DEC@decwrl.ARPA Posted Monday 17th September 1984, 13:53 EDT by DOSADI::BINDER