Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site wateng.UUCP Path: utzoo!watmath!wateng!padpowell From: padpowell@wateng.UUCP (PAD Powell) Newsgroups: net.arch Subject: Re: "When to go to CMOS", or, "Is Schottky dead" Message-ID: <1494@wateng.UUCP> Date: Sun, 30-Sep-84 14:58:02 EDT Article-I.D.: wateng.1494 Posted: Sun Sep 30 14:58:02 1984 Date-Received: Mon, 1-Oct-84 03:38:44 EDT References: <537@turtlevax.UUCP> Organization: U of Waterloo, Ontario Lines: 22 The decisions about LS/S/CMOS have to be made on an individual basis. Currently, it seems to be fairly obvious that ordinary TTL is dead or dying. LS TTL will usually make do for "slow", ie.- < 10 Nsec, things, S is safer if you need speed and margins. Lately I have been observing that S power consumption seems to be going down, while speed is staying the same. Any comments on this? As for CMOS: the curse of CMOS seems to be its limited drive capability. If you run CMOS at 5V, it is usually in the 50-100 Nsec range (you know what I mean), and that is pretty good for lots of things. I have seen specs about some new CMOS drivers that look incredible, but I have not investigated them personally. I have also vicious things to say about CMOS latchup problems. I have just spent a little time discovering that a major failure mode was being caused by the separate supplies on different portions of the system to ramp at different rates. The CMOS board came up after the LS board, and with about 20% probability, at least one part on it would latch up. GRRRRR.... The fix to this problem was not trivial. Patrick ("CMOS! FLIP-FLOP! BIT! BIT! BIT!") Powell