Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site watmath.UUCP Path: utzoo!watmath!jmsellens From: jmsellens@watmath.UUCP (John M Sellens) Newsgroups: net.bugs Subject: Make and Dependant/Command inferences Message-ID: <9441@watmath.UUCP> Date: Wed, 17-Oct-84 19:47:32 EDT Article-I.D.: watmath.9441 Posted: Wed Oct 17 19:47:32 1984 Date-Received: Sun, 21-Oct-84 06:01:09 EDT Organization: U of Waterloo, Ontario Lines: 21 Make behaves in a way that *I* sure didn't expect. Technically, it's probably not a bug, but I think it's kind of weird. If the file b.c exists, the Makefile b.o: a.c echo Hello is interpreted the same as b.o: a.c b.c # !!! echo Hello and, if there were no commands specified (i.e. no "echo Hello"), as b.o: a.c b.c cc $(CFLAGS) -c b.c I had always assumed that make would only try to make inferences about the dependents of a file (in this case 'b.o') if it was not defined on the left side of a line with a colon. And that if I specifically define a file dependency with no commands, that make wouldn't make some up for me. John