Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site hcrvx1.UUCP Path: utzoo!hcrvax!hcrvx1!tom From: tom@hcrvx1.UUCP (Tom Kelly) Newsgroups: net.arch Subject: Re: Arbitrary byte alignment Message-ID: <961@hcrvx1.UUCP> Date: Thu, 11-Oct-84 07:58:32 EDT Article-I.D.: hcrvx1.961 Posted: Thu Oct 11 07:58:32 1984 Date-Received: Fri, 12-Oct-84 02:27:47 EDT References: <426@ima.UUCP> Organization: Human Computing Resources, Toronto Lines: 18 > I suppose it would be possible to have fiendishly clever memory designs > where adjacent words were always in different memory banks so you could > cycle both at the same time. Sounds pretty awful, though, since you have > to determine for each memory reference how many memories to cycle and how > to splice the parts together. As far as I can tell, it's never been > seriously proposed for implementation, except perhaps incidentally in very > large cached architectures such as the IBM 308X. If my memory serves me correctly, the CDC 6600 series had something like this. It was called "Phased Memory" - the configuration we had was described as "40 banks phased". My understanding was that adjacent addresses were in different memory banks, so that memory access could be overlapped. Of course, the 6600 had no byte addressing. If you wanted a byte, you fetched a word and then used shifts and masks. Tom Kelly (416) 922-1937 {utzoo, ihnp4, decvax}!hcr!hcrvx1!tom