Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site utecfa.UUCP Path: utzoo!utcsrgv!utai!uthub!utecfa!jayar From: jayar@utecfa.UUCP (Jonathan Rose SF2202 5036) Newsgroups: ut.vlsi Subject: Seminar on Computer Architecture and VLSI Tools at Stanford Message-ID: <149@utecfa.UUCP> Date: Tue, 5-Jun-84 16:16:20 EDT Article-I.D.: utecfa.149 Posted: Tue Jun 5 16:16:20 1984 Date-Received: Tue, 5-Jun-84 20:35:44 EDT Organization: Engineering, University of Toronto Lines: 27 Cider Seminar Series Part CXL What's Up at Stanford By Paul Chow Room GB 244 Time: 12:05 Date: Friday June 8, 1984 Abstract This will be a very informal description of various happenings and impressions of what's happening at Stanford University in the area of computer architecture, VLSI and whatever else you might care to ask about. A brief description of the next MIPS processor (MIPS- X) will also be given. The goal is to make it go 5-10 times faster than MIPS which means that it will bump into CRAY-1 speeds for "sym- bolic type problems" (non vector). The pro- ject is just starting.