Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site harvard.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxl!houxm!houxz!vax135!floyd!cmcl2!seismo!hao!hplabs!sdcrdcf!sdcsvax!dcdwest!ittvax!decvax!genrad!wjh12!harvard!brownell From: brownell@harvard.UUCP Newsgroups: net.arch Subject: RISC bibliography (longish) Message-ID: <261@harvard.UUCP> Date: Mon, 4-Jun-84 21:39:28 EDT Article-I.D.: harvard.261 Posted: Mon Jun 4 21:39:28 1984 Date-Received: Thu, 7-Jun-84 19:24:03 EDT Organization: Sequoia Systems Inc., Marlborough Mass. Lines: 158 Here are the results of the request I posted for RISC manifestos a week or two ago. Many thanks to Peter Bain (wateng!pdbain), Kevin Kissell (flairvax!kissell), and Hal Perkins (cornell!hal), who provided the references. Such is life that I've not been able to look many of these up, but as you can see most of the sources should not be all that hard to find. They total 24 references; there was only one duplicate. I've left these in the form I received them, both to simplify my life and to reduce any transcription errors. Dave Brownell {allegra,floyd,ihnp4,seismo}!harvard!sequoia!brownell ----------------------------------------------------------------------- %A D.A. Patterson %A P. Garrison %A M. Hill %A D. Lioupis %A C. Nyberg %A T. Sippel %A K. Van Dyke %T Architecture of a VLSI Instruction Cache for a RISC %J Int. Symp. on Computer Architecture %D 1983 %P 108 %A J.A. Fisher %T Very Long Instruction Word Architectures and the ELI 512 %J Int. Symp. on Computer Architecture %D 1983 %P 140 %A G. Radin %T The 801 Minicomputer %J IBM J. Res. Dev. %D 1983 %V 27 %N 3 %P 237 %T MOVE Architecture in Digital Computers %A Daniel Tabak %A G.J. Lipovski %J IEEE Transactions on Computers %V C-29 %N 2 %D February 1980 %P 180-189 %A C.H. Sequin %A D.A. Patterson %T Design and Implementation of RISC I %P 276-298 %A J. Hennessy %A N. Jouppi %A F. Baskett %A J. Gill %T MIPS: A VLSI Processor Architecture %D 1981 %B VLSI Systems and Computations %E H.T. Kung %E R. Sproull %e G. Steele %I Computer Science Press %P 337-346 %A P. Schulthess %A F. Vonaesch %T OPA - A New Architecture for Pascal-Like Languages %P 9 %J ACM Computer Architecture News %V 10 %N 6 %D Dec. 1982 %A M.V. Wilkes %T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer %J Computer Architecture News %I ACM %V 11 %N 5 %D Dec. 1983 %P 5-7 %T Strategies for Managing the Register File in RISC %A Y. Tamir %A C.H. Sequin %J IEEE Trans. on Computers %D Nov. 1983 David A. Patterson, `` A RISCy APPROACH TO COMPUTER DESIGN'' Digest of papers, Spring COMPCON 82 pp. 8-14 IEEE Computer Society press Patterson, D.A., and Ditzel, D.R., ``The Case for the Reduced Instruction Set Computer,'' Computer Architecture News, Vol. 8, No. 6, October 1980, pp. 25-33. Clark, D.W. and Strecker, W.D., ``Comments on `The Case for the Reduced Instruction Set Computer,''' Computer Architecture News, Vol. 8, No. 6, October 1980, pp. 34-38. Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., Gross, T., Baskett, F., and Gill, J., ``MIPS: A Microprocessor Architecture,'' Proceedings from the 15th Annual Workshop on Microprogramming, November 1982, pp. 17-22. ... note: related paper above, in VLSI Systems and Computations Radin, G., ``The 801 Minicomputer,'' Proceedings from the Symposium on Architectural Support for Programming Languages and Operating Systems, March 1982, pp. 39-47. Patterson, D.A. and Sequin, C.H., ``RISC I: A Reduced Instruction Set VLSI Computer,'' Proceedings from the Eighth Symposium on Computer Architecture, May 1981, pp. 443-457. Fitzpatrick, Foderaro, Katevenis, Landman, Patterson, Peek, Peshkess, Sequin, Sherbourne, & Van Dyke, "A RISCy Approach to VLSI," VLSI Design 4th Qtr 1981 Hansen, Mayo, Linton, Murphy, & Patterson, "A Performance Evaluation of the Intel iAPX432," Computer Architecture News, June 1982 bench marks the 432 on the same test programs used to test RISC Foderaro, Van Dyke, & Patterson, "Running RISCs," VLSI Design, Sept/Oct 1982 Katevenis, M.G.H, Sherburne, R.W, Patterson, D.A., and Sequin, C.H., ``The RISC II Micro-Architecture,'' Submitted to the VLSI 83 Conference, August 83, Norway. Larus, J.R., ``A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I,'' Computer Architecture News, Vol. 10, No. 5, September 1982, pp. 10-15. Patterson, D.A. and Piepho, R.S., ``RISC Assessment: A High-Level Language Experiment,'' Proceedings from the Ninth Symposium on Computer Architecture, April 1982, pp. 3-8. Patterson, D.A. and Sequin, C.H., ``A VLSI RISC,'' IEEE Computer, Vol. 15, No. 9, September 1982, pp. 8-21. Foderaro, J.K., Van Dyke, K.S., and Patterson, D.A., ``Running RISCs,'' VLSI Design, September/October, 1982. I suggest you read "Reduced Instruction Set Computer Architectures for VLSI" by Manolis G. H. Katevenis. This is the Ph.D. thesis written by one of the designers of the RISC I & II. It is a tech report UCB/CSD 83/141 from the Computer Science Division (EECS), University of California, Berkeley, CA 94720. There is a nice summary of the RISC project, the rationale behind it, and implementation details of the RISC II chip.