Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 (Tek) 9/26/83; site tektronix.UUCP Path: utzoo!linus!vaxine!wjh12!genrad!decvax!ucbvax!ucbcad!tektronix!scottt From: scottt@tektronix.UUCP Newsgroups: net.micro,net.arch Subject: Re: net.digital: low overhead refresh controller? Message-ID: <2684@tektronix.UUCP> Date: Fri, 1-Jun-84 01:01:28 EDT Article-I.D.: tektroni.2684 Posted: Fri Jun 1 01:01:28 1984 Date-Received: Wed, 6-Jun-84 02:29:15 EDT References: <398@turtlevax.UUCP>, <1179@sun.uucp> Organization: Tektronix, Beaverton OR Lines: 11 I also thought it would be a neat idea to minimize the refresh overhead by remembering which rows had been accessed in the last 2ms by the processor or DMA controller. A few years ago I built a 14 chip TTL implementation to prove out the idea. Then as a project in a VLSI design class I was taking I implemented it on a single MOS IC (about 6K transistors). It was designed to interface to an existing DRAM controller, like an 8203 or 8409. It all worked as expected, but my employer wasn't interested, so I haven't done anything with it for a long time. Scott Trappe tektronix!scottt