Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site intelca.UUCP Path: utzoo!linus!vaxine!wjh12!genrad!decvax!ittvax!dcdwest!sdcsvax!sdcrdcf!hplabs!intelca!kds From: kds@intelca.UUCP Newsgroups: net.micro,net.micro.68k,net.arch Subject: Re: Chip Speed / Re: 68020 vs. 32032, ... Message-ID: <314@intelca.UUCP> Date: Sun, 17-Jun-84 23:40:45 EDT Article-I.D.: intelca.314 Posted: Sun Jun 17 23:40:45 1984 Date-Received: Wed, 20-Jun-84 00:54:41 EDT References: <98@utastro.UUCP> <3606@fortune.UUCP> Organization: Intel, Santa Clara, Ca. Lines: 26 Xref: 1877 66 275 > Traditionally the cpu operations have always been faster > than memory operations, since the same technology > applied to either operation favors the simpler. > >This goes against all I've picked up about hardware >(I acknowledge that I'm primarily a software person). >My understanding is that for the same chip technology, >memory is always easier to design than CPUs, because memory designs >are *simpler* and exhibit so much more regularity than CPU designs. Well, actually, memory chips do tend to be more regular then CPU designs, but the problem is complicated by the sheer number of circuits, buffers, etc., in the memory subsystem as a whole as opposed to the chips themselves. That large memory systems tend to be slower then CPUs points out one reason people use cache memories. System performance can be quite different then chip performance. In addition, different kinds of trade-offs are usually made in the design of memories as opposed to the design of logic circuits, simply because a different kind of problem is trying to be solved. -- Ken Shoemaker, Intel, Santa Clara, Ca. {pur-ee,hplabs,amd,scgvaxd,dual,idi,omsvax}!intelca!kds ---the above views are personal. They may not represent those of Intel.