Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site fortune.UUCP Path: utzoo!watmath!clyde!floyd!harpo!eagle!mhuxl!ihnp4!fortune!phipps From: phipps@fortune.UUCP (Clay Phipps) Newsgroups: net.arch Subject: IBM 801 Cache / Re: RISC perspective Message-ID: <2746@fortune.UUCP> Date: Mon, 12-Mar-84 23:51:13 EST Article-I.D.: fortune.2746 Posted: Mon Mar 12 23:51:13 1984 Date-Received: Tue, 13-Mar-84 20:37:13 EST References: <26@utastro.UUCP> Organization: Fortune Systems, Redwood City, CA Lines: 25 The IBM 801 experimental minicomputer has cache-controlling instructions, for approximately the reasons stated elsewhere in this newsgroup. Particularly compelling were the desire to avoid loading all of a cache line (32 bytes) when a single word (4 bytes) was referenced in a newly-allocated area, such as are used for routine stack frames and i-o buffers. The cache of the 801 uses a "store in cache" rather than "store thru cache" strategy. The only material on the 801 that I've seen outside of IBM is George Radin: "The 801 Minicomputer", *Proc. of the Symposium on Architectural Support for Programming Languages and Operating Systems* (SigArch *Computer Architecture News*, vol. 10, num. 2, March 1982, or *SigPLan Notices*, vol. 17, num. 4, April 1982), p. 39 .. 47. I wonder if that project is still active ... -- Clay Phipps -- {allegra,amd70,cbosgd,dsd,floyd,harpo,hpda,ihnp4, megatest,nsc,oliveb,sri-unix,twg,varian,VisiA,wdl1} !fortune!phipps