Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site kobold.UUCP Path: utzoo!watmath!clyde!burl!ulysses!harpo!decvax!genrad!grkermit!masscomp!kobold!tjt From: tjt@kobold.UUCP Newsgroups: net.arch Subject: Re: Hybrid stack/register machines Message-ID: <284@kobold.UUCP> Date: Fri, 16-Mar-84 06:37:43 EST Article-I.D.: kobold.284 Posted: Fri Mar 16 06:37:43 1984 Date-Received: Sun, 18-Mar-84 07:14:11 EST References: <177@harvard.UUCP> <5935@umcp-cs.UUCP> Organization: Masscomp, Westford, MA Lines: 9 Mark Weiser (ucmp-cs!mark) claims that "cache is slower than registers because register instructions are shorter than cache instructions." This is true for register-machine architectures (pdp-11, vax, 68000, ...), but would not be true of a pure stack machine. The only operators with explicit addresses would be PUSH and POP -- all others manipulate the values on the top of the stack. -- Tom Teixeira, Massachusetts Computer Corporation. Westford MA ...!{ihnp4,harpo,decvax}!masscomp!tjt (617) 692-6200 x275