Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10 5/3/83; site pyuxss.UUCP
Path: utzoo!watmath!clyde!floyd!whuxle!spuxll!abnjh!u1100a!pyuxn!pyuxww!pyuxss!aaw
From: aaw@pyuxss.UUCP (Aaron Werman)
Newsgroups: net.arch
Subject: Re: RISC perspective - (nf)
Message-ID: <291@pyuxss.UUCP>
Date: Mon, 12-Mar-84 10:49:34 EST
Article-I.D.: pyuxss.291
Posted: Mon Mar 12 10:49:34 1984
Date-Received: Wed, 14-Mar-84 07:09:44 EST
References: <2736@fortune.UUCP>
Organization: Bell Communications Research, Piscataway N.J.
Lines: 18

To add my wish list -
	First a note -the TMS9900 series was one of the slowest
microprocessors ever publicly sold, because although context switching
and process switching did not take much time, the lack of registers
slowed it to a crawl.

How about an architecture with mixed memory - that is, have
subroutines consisting of a small chunk of very fast memory trailed by
the rest of the subroutine contained in normal memory. The obvious
place for this "uncache" would be inside the memory controller.
This scheme would allow fast context switching as well as real time
program execution.
The problem with nonregister architectures though is most visible in 0
address (pure stack) machines, which inherently clog memory busses
rather than perform useful function. Some algorithms are enhanced by
registers, others don't need 'em.
			{harpo,houxm,ihnp4}!pyuxss!aaw
			Aaron Werman