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Path: utzoo!watmath!clyde!floyd!harpo!seismo!hao!hplabs!hp-pcd!orstcs!nathan
From: nathan@orstcs.UUCP
Newsgroups: net.arch
Subject: RISC perspective
Message-ID: <2800001@orstcs.UUCP>
Date: Thu, 1-Mar-84 05:53:00 EST
Article-I.D.: orstcs.2800001
Posted: Thu Mar  1 05:53:00 1984
Date-Received: Sun, 4-Mar-84 03:26:50 EST
Organization: Oregon State University - Corvallis, OR
Lines: 16
Nf-ID: #N:orstcs:2800001:000:754
Nf-From: orstcs!nathan    Mar  1 02:53:00 1984

We've seen a lot lately about RISC architectures, and a
bunch of people down at Berkeley did a chip, and Pyramid
Computers has a box out that they claim far outperforms a Vax.

I would like to make the claim that a RISC with a medium-to-large
instruction cache could be called a "virtual-microcode" machine.
Since on a RISC all the complicated operations are implemented with
a somewhat brain-damaged subroutine call, the subroutines that
implement what would be instructions on another architecture tend
to be in the cache all the time.  This includes the Enter and Exit
operations, loop operations, and the like; esoterica such as long
divides would sit out in main memory until needed.

Does anyone have any objection to this analogy?

	Nathan Myers