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From: hal@cornell.UUCP (Hal Perkins)
Newsgroups: net.arch
Subject: Re: RISC perspective
Message-ID: <6854@cornell.UUCP>
Date: Sun, 11-Mar-84 16:48:20 EST
Article-I.D.: cornell.6854
Posted: Sun Mar 11 16:48:20 1984
Date-Received: Mon, 12-Mar-84 05:40:07 EST
References: <2736@fortune.UUCP>
Organization: Cornell Univ. CS Dept.
Lines: 19

The IBM 801, which also has a simple register-register instruction
set like the RISC, has explicit instructions to control the cache.
For example, if the program is about to store the registers into a
block of memory, the instructions can be used to prevent the cache
from fetching the old contents of the storage line when the first
byte of the line is referenced.

Now, a question.  The only thing I've seen on the 801 is the paper
in the 1982 conference on hardware support for high-level languages
(printed in a special issue of SIGPLAN Notices/SIGARCH News).  This
was later revised and printed in the IBM Journal of R&D.  Has anyone
seen any other information about this?  I'd particularly like to see
a "Principles of Operation" or architecture manual for the 801, but
I'm afraid that information is probably still classified IBM Top
Secret.


Hal Perkins                         UUCP: {decvax|vax135|...}!cornell!hal
Cornell Computer Science            ARPA: hal@cornell  BITNET: hal@crnlcs