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Path: utzoo!watmath!clyde!floyd!harpo!seismo!hao!hplabs!sri-unix!SHahn@SUMEX-AIM.ARPA
From: SHahn@SUMEX-AIM.ARPA
Newsgroups: net.micro
Subject: Re: 68K vs. 16K vs. VAX
Message-ID: <17023@sri-arpa.UUCP>
Date: Wed, 29-Feb-84 18:17:15 EST
Article-I.D.: sri-arpa.17023
Posted: Wed Feb 29 18:17:15 1984
Date-Received: Sun, 4-Mar-84 03:29:59 EST
Lines: 20

From:  Sam Hahn 

On Monday afternoon, I happened to stray into a room at Stanford where someone
from DEC was giving a presentation on a 5-chip implementation of the VAX
architecture.  Performance is very close to the chip described by Larry Seiler,
with roughly the same limitations on instruction set and datatypes.  Much is in
microcode ROM.  An optional FPA chip is available.  Impressions were that
the 5-chip group and the 1-chip group were highly competitive but parallel,
and generated working versions within days of each other (2 days, I think he
said).  Interesting, but not tremendously so until we find out what DEC intends
to do with these new implementations.  The performance claimed was very, very
close to that of the 780, within <10%, it appeared, across categories of
cache hits, arithmetic, move, and branch instructions (from what I remember).
DEC doesn't yet have any yield figures, since these chips are so new.

P.S.  This is all from organic memory (mine), which I've never claimed was
infallible.  I've probably missed a lot, but you'll probably be reading about
this pretty soon.

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