Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site uw-june Path: utzoo!watmath!clyde!floyd!harpo!decvax!ucbvax!ucbcad!tektronix!uw-beaver!uw-june!rling From: rling@uw-june (Robert Ling) Newsgroups: net.micro.16k Subject: 16K Central Processor Message-ID: <1102@uw-june> Date: Fri, 9-Mar-84 19:38:40 EST Article-I.D.: uw-june.1102 Posted: Fri Mar 9 19:38:40 1984 Date-Received: Wed, 14-Mar-84 07:34:03 EST Distribution: net.micro Organization: U. Washington, Computer Sci Lines: 30 Does anyone have any information or know of a source where I could get some information on the following about the NSC 16k series microprocessors and its slaves? - There is an eight byte instruction queue in the Pc, but there is no mention of any pipelineing in the instruction decoding process. - Their literature hints of a set of 'shadow' registers which saves the states of other general registers when an instruction is initiated. How many of these registers are there and which of the general registers do they save? - The width of the micro-instruction word and the size of the Control Store. - Is the Floating Point Unit pipelined? (Since there is a data queue) Please reply to me directly. Any information would be greatly appreciated. If there is sufficient response, I will post a summary. Robert Ling. ...decvax!microsoft!uw-beaver!uw-june!rling