Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site umcp-cs.UUCP Path: utzoo!watmath!clyde!floyd!harpo!seismo!rlgvax!cvl!umcp-cs!chris From: chris@umcp-cs.UUCP Newsgroups: net.arch Subject: Re: Use Of Multiple Register Sets / Re: RISC perspective Message-ID: <5885@umcp-cs.UUCP> Date: Tue, 13-Mar-84 21:04:40 EST Article-I.D.: umcp-cs.5885 Posted: Tue Mar 13 21:04:40 1984 Date-Received: Wed, 14-Mar-84 19:53:56 EST References: <2736@fortune.UUCP> <2747@fortune.UUCP> Organization: Univ. of Maryland, Computer Science Dept. Lines: 41 Actually, if you have hardware support for registers that "fall off the end of the chip", then process context switch doesn't have to be difficult, even for thousands of registers. All you need is a little clever trickery (and probably lots more silicon). The basic idea is to treat registers as a funny kind of cache. Example: r0 r1 ... r9 r10 r11 r12 ... r225 r226 ... r781 --------mine-------- ---0x43210--- ---0x44444--- (therefore valid) mem addr mem addr (actually one per reg) If each register has a memory address (either physical memory or the virtual address of a given process, with a possible "no address") then process context switch is very simple: just fiddle with the "Valid Pointer" (who says in the above picture that r11 is the last valid register). The registers (r0-r11) are already attached to the right process (since they have to have a mem address already assigned in case they "fall off" because of n thousand subroutine calls). The Valid Pointer gets reset to include no registers and gets his mem address value changed to the new process. Whenever you touch a register, if it's not valid the following sequence of events happens: if was_assigned_to_other_process then store_at_other_process_memory_address read_from_my_memory_address elif was_assigned_to_my_process then fancy_trickery_to_try_to_avoid_memory_references else read_from_my_memory_address fi make_register_valid Anyway, the result should be a very inexpensive process context switch with a little bit of extra overhead per register fetch/store (which you can probably do in parallel with something else you have to do anyway). Hm, I wonder if I can patent this?