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From: mark@umcp-cs.UUCP
Newsgroups: net.arch
Subject: Re: Hybrid stack/register machines
Message-ID: <5935@umcp-cs.UUCP>
Date: Thu, 15-Mar-84 13:54:43 EST
Article-I.D.: umcp-cs.5935
Posted: Thu Mar 15 13:54:43 1984
Date-Received: Fri, 16-Mar-84 02:40:25 EST
References: <177@harvard.UUCP>
Organization: Univ. of Maryland, Computer Science Dept.
Lines: 7

Cache is slower than registers because register instructions are shorter
than cache instructions (which must reference a real memory address).
Now let me see, if the instructions are also cached, this is less important,
but at every branch it matters again for a little while.
-- 
Spoken: Mark Weiser 	ARPA:	mark@maryland
CSNet:	mark@umcp-cs 	UUCP:	{seismo,allegra,brl-bmd}!umcp-cs!mark