Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site kobold.UUCP Path: utzoo!watmath!clyde!floyd!harpo!decvax!genrad!grkermit!masscomp!kobold!tjt From: tjt@kobold.UUCP Newsgroups: net.micro Subject: Re: Large Dual Ported Memories - (nf) Message-ID: <282@kobold.UUCP> Date: Tue, 13-Mar-84 09:29:23 EST Article-I.D.: kobold.282 Posted: Tue Mar 13 09:29:23 1984 Date-Received: Wed, 14-Mar-84 20:11:12 EST References: <6033@uiucdcs.UUCP> Organization: Masscomp, Westford, MA Lines: 12 Well, I don't know about *large* dual ported memories, but it is quite common to use dual ported memories for registers in CPU's. It is not done by address interleaving, but rather by duplicating the memory. This allows true, independent reads, but any write must be done to *both* memories. Again, there is a cach in that you need to know what kind of accesses will be performed. Inside a CPU, the use of multiport register files is to feed one register as one input to the ALU, another register to the other ALU input, and then write the result back. The reads should be simultaneous, but will not overlap with the write. -- Tom Teixeira, Massachusetts Computer Corporation. Westford MA ...!{ihnp4,harpo,decvax}!masscomp!tjt (617) 692-6200 x275