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From: dollas@uiuccsb.UUCP
Newsgroups: net.micro
Subject: Re: Large Dual Ported Memories - (nf)
Message-ID: <6033@uiucdcs.UUCP>
Date: Mon, 5-Mar-84 22:33:17 EST
Article-I.D.: uiucdcs.6033
Posted: Mon Mar  5 22:33:17 1984
Date-Received: Wed, 7-Mar-84 00:28:57 EST
Lines: 35

#R:sri-arpa:-1705300:uiuccsb:4400051:000:1999
uiuccsb!dollas    Mar  5 07:35:00 1984

   To the best of my knowledge there is no such beast as a  multiport 
memory when one goes down to the hardware-hardware level. The way it
can be faked is by address interleaving, ie rearrangement of the addresses
of the memory requests in such a way that two addresses that need to be
accessed at one time are on different chips. However there is a catch: 
you have to know in advance (from the architecture) what kind of 
accesses you need to do. For a von Neumann machine it is not that bad 
because usually the requests are for consecutive addresses (say, to
load a program, page swapping, etc), in which case one needs only to 
make consecutive words be physically separated on the chip level (a 
simple example is to have odd/even words separated).
   In a dataflow machine the access requests depend of course on the
architecture. In a machine in which virtually all
address combinations can occur it seems to me that the best solution
is to make a multiport (with several ports) memory on the stochastic
model that will yield the fewest conflicts. With any realistic 
constraints (cost, complexity, etc) the model will not be perfect
(no conflicts) but you may be surprised at how well such a model can do.
Naturally the smallest the size of each bank that will be 'tied' with a
memory request the better you will do, but with a higher overhead.
It may also be worth to see if your memory accesses are in predetermined
patterns, in which case a solution similar to that discussed in the
previous paragraph may do the trick...
   Finally, in terms of multiplexing the addresses I think that it may
be possible to do all the interleaving on the PC board level (thus
saving the delay of multiplexing with active components).
   Good Luck!

                                            Apostolos Dollas
                                           Dept. of Comp. Sci.
                                             U. of Illinois
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