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From: emjej@uokvax.UUCP
Newsgroups: net.arch
Subject: Re: Hybrid stack/register machines - (nf)
Message-ID: <6316@uiucdcs.UUCP>
Date: Thu, 29-Mar-84 00:15:30 EST
Article-I.D.: uiucdcs.6316
Posted: Thu Mar 29 00:15:30 1984
Date-Received: Fri, 23-Mar-84 08:45:21 EST
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#R:harvard:-17700:uokvax:9900009:000:980
uokvax!emjej    Mar 20 09:24:00 1984

/***** uokvax:net.arch / harvard!brownell /  1:35 am  Mar 15, 1984 */
Has anybody produced "stack" machines that keep some large portion of
the top frame in the processor, instead of memory?  So to speak -- in
"registers"?  The number of frame elements in the processor could be fixed,
or they could be in a small, dedicated, high speed cache.  Highspeed
register flushing would be a must; maybe it could be done in parallel
with setting up call frames.
/* ---------- */

This is something that Elliot Organick mentions in his book on the
B5500 as a possible improvement (I think the top n words, for some
small n, are in faster memory; he proposed increasing n). Can someone
from Burroughs tell us whether it is done in some of the B6700/6800
machines?

It's also, if I understand correctly, what Steve Johnson has been
working with for a while; there was a joint SIGARCH/SIG(PLAN?)
conference last year, I believe, containing a paper of his with some
results.

					James Jones