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From: brownell@harvard.UUCP (Dave Brownell)
Newsgroups: net.arch
Subject: Hybrid stack/register machines
Message-ID: <177@harvard.UUCP>
Date: Wed, 14-Mar-84 07:38:36 EST
Article-I.D.: harvard.177
Posted: Wed Mar 14 07:38:36 1984
Date-Received: Thu, 15-Mar-84 07:18:26 EST
Organization: Aiken Computation Lab, Harvard
Lines: 23

That comment about context switching speed on stack machines, versus
the speed of access to registers (especially on the TI 9900 microprocessor)
brought up something I've been wondering for some time.

Has anybody produced "stack" machines that keep some large portion of
the top frame in the processor, instead of memory?  So to speak -- in
"registers"?  The number of frame elements in the processor could be fixed,
or they could be in a small, dedicated, high speed cache.  Highspeed
register flushing would be a must; maybe it could be done in parallel
with setting up call frames.

It seems to me that this approach could get many of the benefits of both
stack machines (simpler compiler technology) and register machines (fast
access for frequently used variables).  I know that some compiler manipulations
that I don't see done very often (does UNIX mislead me?) simulate this, and
that a normal cache is still slower than registers.  Am I missing something?
Is there a way less radical than RISC to use simple compiler and hardware
technology and still get high performance?



	Dave Brownell
	...{decvax,linus,sdcsvax}!genrad!wjh12!harvard!brownell