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Path: utzoo!linus!philabs!cmcl2!floyd!vax135!cornell!uw-beaver!tektronix!tekecs!orca!andrew
From: andrew@orca.UUCP
Newsgroups: net.arch
Subject: uP architecture and the NOVA
Message-ID: <1358@orca.UUCP>
Date: Mon, 4-Jul-83 13:40:18 EDT
Article-I.D.: orca.1358
Posted: Mon Jul  4 13:40:18 1983
Date-Received: Thu, 7-Jul-83 10:50:51 EDT
Lines: 26

I can't believe that people are holding up the NOVA instruction set as
a design to be emulated!  This is the machine where you cannot cram a
16-bit address into any sort of instruction; the most you have are four
flavors of short displacements: relative to either of two registers,
relative to PC, or located in low memory ("page zero").  The
convolutions you have to go through to write (or generate) machine code
are painful.  You want to call a distant subroutine?  Plant a pointer
to it, somewhere close to your "call" instruction, and do an indirect
reference.  Duplication of commonly-used constants is rampant because
you can only refer to constants within plus-or-minus 128 words.

Addresses refer to 16-bit words, rather than to bytes.  At first glance
this looks like a trade-off of byte-addressability for a double-sized
address space, right?  Nope, addresses are *fifteen* bits wide ... the
high bit of a sixteen bit word is ignored (at east on the original NOVA
design).

Sure, a horizontal instruction set looks elegant, but just try writing
a code generator when you have a flock of users who want absolutely
optimal code.  The complexity of the task is exponential with the
number of independent operations which a single instruction can perform.

Give me an 8080 any day!

  -- Andrew Klossner   (decvax!teklabs!tekecs!andrew)  [UUCP]
                       (andrew.tektronix@rand-relay)   [ARPA]