Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!linus!genrad!mit-eddi!mit-vax!eagle!mhuxt!mhuxi!cbosgd!ihnp4!ixn5c!inuxc!pur-ee!uiucdcs!bcase From: bcase@uiucdcs.UUCP Newsgroups: net.arch Subject: Re: RISC - (nf) Message-ID: <2313@uiucdcs.UUCP> Date: Mon, 27-Jun-83 23:26:04 EDT Article-I.D.: uiucdcs.2313 Posted: Mon Jun 27 23:26:04 1983 Date-Received: Wed, 29-Jun-83 10:51:27 EDT Lines: 34 #R:tekecs:-145500:uiucdcs:27800011:000:1529 uiucdcs!bcase Jun 27 19:03:00 1983 First, to my mind, using 'RISC' may mean only the Berkeley RISC machine, but it is rapidly becomming a generic term used to describe an architecture which is designed to execute simple instructions quickly. For some of the 'RISC'-like machines, there is very little difference between the language of the machine and traditional microcode; it just depends on which one you are talking about. Compiling for the Stanford MIPS is very much like compiling to microcode. Rather than make this a dissertation, please accept the following as recommended readings: "The Case for the Reduced Instruction Set Computer," Computer Arch. News, Vol. 8, No. 6, Oct. 1980. "RISC I: A Reduced Instruction Set VLSI Computer," Proceedings from the Eighth Symp. on Comp. Arch., May 1981. "Comments on 'The Case for the Reduced Instruction Set Computer,'" CAN, Vol. 8, No. 6, Oct. 1980. "MIPS: A Microprocessor Architecture," Proceedings from the 15th Workshop on Microprogramming, Nov. 1982. "The 801 Minicomputer," Proceedings from the Symp. on Arch. Support for Programming Langs. and OSs, March 1982. There are many more, especially by Patterson, but they are mostly repetitive. There is one in VLSI design which describes how the first RISC Is performed. Have fun. This is an interesting area; everybody seems to think that everyone else's design is wrong ("They'll never succeed, they're doing it all wrong."). (I didn't intend to show favoritism in my list of references, if anyone has any other suggestions, I want to read 'em.)