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Path: utzoo!linus!decvax!harpo!gummo!whuxlb!jph
From: jph@whuxlb.UUCP
Newsgroups: net.micro.pc
Subject: Re: parity error interrupts - (nf)
Message-ID: <1245@whuxlb.UUCP>
Date: Tue, 26-Jul-83 21:02:57 EDT
Article-I.D.: whuxlb.1245
Posted: Tue Jul 26 21:02:57 1983
Date-Received: Wed, 27-Jul-83 08:47:43 EDT
Sender: jph@whuxlb.UUCP
Organization: Bell Labs, Whippany
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#R:tucc:-390100:whuxlb:6400007:000:235
whuxlb!jph    Jul 26 21:02:00 1983

On a parity error, an INT 2 (NMI) is executed. When I/O
port 62H is checked and bit 6 or 7 is set, then a
parity error has occurred. If you look on page A-10 of
the Tech Ref. Manual, you will find the code that
handles this condition.