Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10 5/3/83; site ucbcad.UUCP Path: utzoo!linus!decvax!tektronix!ucbcad!ucbesvax.turner From: ucbesvax.turner@ucbcad.UUCP Newsgroups: net.arch Subject: loop registers? - (nf) Message-ID: <251@ucbcad.UUCP> Date: Tue, 12-Jul-83 07:48:44 EDT Article-I.D.: ucbcad.251 Posted: Tue Jul 12 07:48:44 1983 Date-Received: Tue, 12-Jul-83 20:12:43 EDT Sender: notes@ucbcad.UUCP Organization: UC Berkeley, CAD Group Lines: 24 #N:ucbesvax:12800005:000:781 ucbesvax!turner Jul 11 19:06:00 1983 Does anyone out there know of a processor with a "loop branch point" register--i.e., a register which holds a pc-value for continuation of loops? To give a simple example of string copy: ... ! a0,a1 with char pointers: lea bpr, pc ! next instruction loc -> loop branch point movb @a0+, @a1+ ! copy byte, post-incrementing loopnz ! pc <- lpb if byte was nonzero ... Of course, I suppose you could just say "jnz a2" instead, using a2 as a branch-point-register, if you really wanted to get into tricky code optimizations. It seems preferable to garbaging up the architecture with special registers and instructions. As an alternative question, then: does anyone know of code generators which do such optimizations? Michael Turner ucbvax!ucbesvax.turner