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From: mkg@whuxlb.UUCP
Newsgroups: net.micro.pc
Subject: Re: parity error interrupts - (nf)
Message-ID: <1253@whuxlb.UUCP>
Date: Thu, 4-Aug-83 21:46:38 EDT
Article-I.D.: whuxlb.1253
Posted: Thu Aug  4 21:46:38 1983
Date-Received: Fri, 5-Aug-83 22:37:41 EDT
Sender: mkg@whuxlb.UUCP
Organization: Bell Labs, Whippany
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#R:tucc:-390100:whuxlb:6400007:000:235
whuxlb!jph    Jul 26 21:02:00 1983

On a parity error, an INT 2 (NMI) is executed. When I/O
port 62H is checked and bit 6 or 7 is set, then a
parity error has occurred. If you look on page A-10 of
the Tech Ref. Manual, you will find the code that
handles this condition.