From: utzoo!decvax!harpo!npoiv!rah Newsgroups: net.micro.68k Title: Re: 68k vs. 8086 - (nf) Article-I.D.: npoiv.1969 Posted: Tue Feb 15 14:11:16 1983 Received: Fri Feb 18 03:49:25 1983 References: ucbcad.601 grkermit.295 I assume that you are talking about an ad such as is on page 171 of the Feb. 10th "Electronics." You have to read the fine print. a) The comparison is between an iAPX286 and a M68000. By Intel's own admission, an iAPX 286 is 3 times as fast as an iAPX 86 (8086) at the same clock speed. b) In the add the 68000 is .28 to .49 of the 286, so it is indeed faster than an 8086. c) In the ad, note the bus speeds: The iAPX 286 is cycling the bus every 2 clock cycles (i.e. 250 nanoseconds / bus cycle) while the M68000 is cycling the bus every 6 clock cycles (i.e. 750 nano-seconds). d) The reason for c) is that the M68000 is assumed to use a M68451 which imposes (in their calculations) 2 wait states on the M68000. As is demonstrated by the SUN boards, with a clever memory management scheme you don't need to impose wait states. e) From d) you can multiply the numbers given for the M68000 by 1.5, or from c) you can multiply the numbers by 3.0 if you assume equal bus cycle times. f) Note that a 250 nanosecond bus cycle is awfully fast to keep up, typically you add some overhead to the basic cycle times of dynamic RAMS in getting the data to the bus or off of it. g) More importantly, the comparisons don't deal with any benchmarks which need to access large arrays, for example a 1024x1024 display bitmap which is 2 to the 17th bytes large. Note that the Intel iAPX 286 can't directly address that large a space, it must load and unload segment registers, while the M68000 could directly address it. h) As always, let the reader beware (caveat lector?) Rich Hammond