From: utzoo!decvax!harpo!utah-cs!sask!hssg40!peachey
Newsgroups: net.micro
Title: Re: Lisa benchmark
Article-I.D.: hssg40.279
Posted: Mon Feb  7 09:49:03 1983
Received: Fri Feb 11 00:35:11 1983

	Let's look at these CPU benchmarks logically for a moment.
	First of all, setting an integer to 10 million is not very
	useful if the integer size is 16 bits.  On a 16 bit
	machine, the maximum number of loops before hitting zero
	is 64K, which gives the 16 bit machine an advantage of
	more than 152 times.  This makes it easy for the Z80 to
	do the benchmark in a phenomenally short time.

	At 5 MHz with no wait states, a hand-optimized loop on
	the MC68000 should take about 3.6 microseconds.  Thus,
	36 seconds would be a reasonable time for 10 million
	loops.  Presumably the C compiler didn't generate as
	good code as I did, or some other hardware/software
	factor interfered, but the Lisa time of 56.7 seconds
	is still very reasonable.

	I don't recall which model of Series/1 processor
	IBM had on display at UNICOM.  Judging from the
	average instruction time described in their brochure,
	which ranges from 9.3 microseconds for the slow
	processor, to 2.65 microseconds for the fast one,
	the Series/1 is quite slow.  Even so, if the Series/1
	C compiler is using a 16-bit integer, you would
	expect a run time of a few seconds for the benchmark.
	If it is using a 32-bit integer, run time might
	be as long as ten minutes or so.  However, I suspect
	that it's more likely that something broke in the
	benchmark, and put it into an nonterminating loop.

	In case you're interested, here are some more measurements
	of run times on 10000000 loops with a "long" (32 bit) counter:

	LSI-11/23          206 seconds
	PDP-11/40          171 seconds (300 ns MOS memory)
	Z8000               63 seconds (Zilog System 8000;unknown clock rate)
	PDP-11/70           60 seconds
        10 MHz MC68000      18 seconds (no wait states)
	VAX-11/780          11 seconds

	Of course, the 16-bit machines in this test had to
	do more instructions in each loop to simulate 32-bit
	integers.

				Darwyn Peachey
				Hospital Systems Study Group

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