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Forum: Commodore 8-bit
 Topic: CMD HD Controller board
CMD HD Controller board [message #384584] Tue, 25 June 2019 02:18
charlesgutman is currently offline  charlesgutman
Messages: 71
Registered: March 2013
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Does anyone know where I might get a hold of a CMD HD controller board?

Thanks so much
Forum: Apple II
 Topic: 3.5 AE or Apple drive needed for llgs...
Re: 3.5 AE or Apple drive needed for llgs... [message #384586 is a reply to message #384576] Tue, 25 June 2019 05:35
Anonymous
Karma:
Originally posted by: groink_hi

Sounds like the infamous gear shattered.
https://www.youtube.com/watch?v=tVXHScWcnUA
 Topic: ProDOS 3.2.1
Re: ProDOS 3.2.1 [message #384583 is a reply to message #384575] Tue, 25 June 2019 00:31
Jeff Blakeney is currently offline  Jeff Blakeney
Messages: 90
Registered: September 2013
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On 2019-06-24 11:13 a.m., fadden wrote:
> Up next, Pro DOS 3.3, the professional version of DOS 3.3, based on
> DOS 4.1. It ships on the back side of a floppy with ProDOS 3.3.
>
> It also ships with GS/OS SYSTEM 6.0.4, which is like System 6.0.4 but
> all the filesystems are case-sensitive. When saying it out loud
> you're supposed to bounce on your toes while saying "SYSTEM" to make
> it clear which version you mean.
>
> (Maybe we can identify variants by appending initials to the base
> version instead? Or at least version the OS kernel separately from
> the disk contents. Maybe we can give them code names like Linux
> distributions... ProDOS Leaping Lizard.)

Please do make sure that these versions are labelled very clearly. I
have absolutely no interest in having an operating system where the file
names are case sensitive. The only reason I can see it having been
implemented in the first place was lazy coders not wanting to convert
file names to all one case before doing comparisons for equality. Why
on earth would I want to have a file called "System" be different than a
file called "SYSTEM" or one of a whole lot of other variations. In
English, the word "System" means the same regardless of what
capitalization of letters you use.
Re: ProDOS 3.2.1 [message #384589 is a reply to message #384583] Tue, 25 June 2019 09:29
Antoine Vignau is currently offline  Antoine Vignau
Messages: 1634
Registered: October 2012
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Andy: I like that
Jeff: it was a joke from Andy

Antoine
Re: ProDOS 3.2.1 [message #384590 is a reply to message #384589] Tue, 25 June 2019 10:36
Jeff Blakeney is currently offline  Jeff Blakeney
Messages: 90
Registered: September 2013
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On 2019-06-25 9:29 a.m., Antoine Vignau wrote:> Andy: I like that
> Jeff: it was a joke from Andy
Sorry, I didn't catch it. It was late and I was tired and I had checked
my messages just before going to bed.

However, my opinion on case sensitive file names remains the same. :)
Re: ProDOS 3.2.1 [message #384591 is a reply to message #384590] Tue, 25 June 2019 13:24
Antoine Vignau is currently offline  Antoine Vignau
Messages: 1634
Registered: October 2012
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Senior Member
No worries, Jeff.

Ahem... my DOS 3.4 (a real thing at http://www.brutaldeluxe.fr/projects/dos34/) is case sensitive to typing but case insensitive (all uppercase) in I/O

You can: bload LoGo
it will load LOGO
It does not store LoGo in the catalog

av
Re: ProDOS 3.2.1 [message #384594 is a reply to message #384591] Tue, 25 June 2019 15:28
Anonymous
Karma:
Originally posted by: Brian Patrie

On 25/06/2019 12.24, Antoine Vignau wrote:
> No worries, Jeff.
>
> Ahem... my DOS 3.4 (a real thing at http://www.brutaldeluxe.fr/projects/dos34/) is case sensitive to typing but case insensitive (all uppercase) in I/O
>
> You can: bload LoGo
> it will load LOGO
> It does not store LoGo in the catalog
>
> av

As a Linux user, i'm used to case-preserving, case-sensitive; but i like
case-preserving, case-insensitive (i.e. mixed case is stored, but
matching case is not required).
Forum: Computer Folklore
 Topic: Computer museum proposed for Philadelphia
Re: Computer museum proposed for Philadelphia [message #384585 is a reply to message #384578] Tue, 25 June 2019 06:35
John Levine is currently offline  John Levine
Messages: 901
Registered: December 2011
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In article <22af5c36-aaad-4eba-bf3f-751237f946d8@googlegroups.com> you write:
> article describes proposal
> https://www.inquirer.com/business/eniac-computer-pennsylvani a-university-silicon-valley-museum-20190619.html

Gruber marvels, noting he just spent $245 on a grocery-bag-size
Samsung SSD that holds two terabytes -- two million megabytes.

Where do you get an SSD that big? (Or, I supose, where do you get a
grocery bag that small?)

--
Regards,
John Levine, johnl@iecc.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
Re: Computer museum proposed for Philadelphia [message #384587 is a reply to message #384578] Tue, 25 June 2019 08:14
John Levine is currently offline  John Levine
Messages: 901
Registered: December 2011
Karma:
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> On 2019-06-25, John Levine <johnl@taugh.com> wrote:
>> In article <22af5c36-aaad-4eba-bf3f-751237f946d8@googlegroups.com> you write:
>>> article describes proposal
>>> https://www.inquirer.com/business/eniac-computer-pennsylvani a-university-silicon-valley-museum-20190619.html
>>
>> Gruber marvels, noting he just spent $245 on a grocery-bag-size
>> Samsung SSD that holds two terabytes -- two million megabytes.
>>
>> Where do you get an SSD that big?
>
> Pick one of the 39,100,000 results that a Google search for "2Tb SSD"
> yields.

I meant physically that big. (See the parenthesized snark you snipped
out.) The SSDs I use are about the size of a pack of cards. I've been
to Philadelphia -- the grocery bags aren't that small.



--
Regards,
John Levine, johnl@iecc.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
Re: Computer museum proposed for Philadelphia [message #384588 is a reply to message #384578] Tue, 25 June 2019 08:34
Quadibloc is currently offline  Quadibloc
Messages: 3552
Registered: June 2012
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On Monday, June 24, 2019 at 9:26:49 PM UTC-6, Dave Garland wrote:
> On 6/24/2019 8:56 PM, Quadibloc wrote:
>> As long as MOVE doesn't take control of a building near the museum...
>
> You mean, the incident where the police torched a building where the
> resulting fire ended up destroying 63 houses, killing 11 people
> including 5 children?

The 5 children were murdered by MOVE, being infants deliberately placed in the
building. And the resulting fire only ended up destroying 63 buildings because
people in MOVE shot at the firefighters.

That doesn't exonerate the city of Philadelphia from all blame, but it is indeed
intolerable for any building to exist that the police are unable to enter - so
if a wrecking ball would be shot at, something one can do from the air would
seem like the only alternative.

John Savard
 Topic: Sixteen general registers, 15 index registers
Re: 360 supercomputers, was Sixteen general registers, 15 index registers [message #384592 is a reply to message #383501] Tue, 25 June 2019 14:17
Alan Bowler is currently offline  Alan Bowler
Messages: 167
Registered: July 2012
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On 2019-05-02 1:29 p.m., timcaffrey420@gmail.com wrote:
> (And really, on the CDC 6000 series there was only one PP, it
> was just multiplexed (barrel execution) by 10).
> 4K 12 bit words, 18 bit accumulator.

Isn't that called hyper-threading today?
Re: 360 supercomputers, was Sixteen general registers, 15 index registers [message #384593 is a reply to message #384592] Tue, 25 June 2019 14:25
scott is currently offline  scott
Messages: 3289
Registered: February 2012
Karma:
Senior Member
Alan Bowler <atbowler@thinkage.ca> writes:
> On 2019-05-02 1:29 p.m., timcaffrey420@gmail.com wrote:
>> (And really, on the CDC 6000 series there was only one PP, it
>> was just multiplexed (barrel execution) by 10).
>> 4K 12 bit words, 18 bit accumulator.
>
> Isn't that called hyper-threading today?

Not accuratly, no.

Hyperthreading simply overprovisions the superscaler nature of the
processor pipeline with additional register sets[*] (and internal
resources such as fifos and scoreboards) to create the illusion of multiple processors on a
single core.

[*] Including all (or most) of the privileged registers such
as the page table base register &c.
Re: 360 supercomputers, was Sixteen general registers, 15 index registers [message #384595 is a reply to message #384593] Tue, 25 June 2019 14:59
Quadibloc is currently offline  Quadibloc
Messages: 3552
Registered: June 2012
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On Tuesday, June 25, 2019 at 12:25:49 PM UTC-6, Scott Lurndal wrote:
> Alan Bowler <atbowler@thinkage.ca> writes:
>> On 2019-05-02 1:29 p.m., timcaffrey420@gmail.com wrote:
>>> (And really, on the CDC 6000 series there was only one PP, it
>>> was just multiplexed (barrel execution) by 10).
>>> 4K 12 bit words, 18 bit accumulator.
>>
>> Isn't that called hyper-threading today?
>
> Not accuratly, no.
>
> Hyperthreading simply overprovisions the superscaler nature of the
> processor pipeline with additional register sets[*] (and internal
> resources such as fifos and scoreboards) to create the illusion of multiple processors on a
> single core.
>
> [*] Including all (or most) of the privileged registers such
> as the page table base register &c.

Barrel execution is very similar to simultaneous multiprocessing. Both create
the illusion of multiple computers on one physical CPU, both require multiple
sets of registers.

In fact, I would be inclined to say that barrel execution _is_ an example of
SMP. Not all SMP is barrel execution, however: barrel execution meant that the
CDC 6600's peripheral processors all ran at 1/10 the speed of the underlying
hardware even if some of them were idle - so the PP hardware always cycled
through the 10 virtual PPs in strict succession.

On an Intel processor with Intel Hyperthreading brand SMP, or on a Ryzen with
SMP, if there is no second thread, the core spends all its time on the first
one.

Barrel execution, thus, is the simplest and most primitive form of SMP. And, of
course, as the architecture of the peripheral processor was that of a CDC 1604,
it didn't have a pipeline, or page tables, to worry about - just an accumulator
and a carry bit.

John Savard
Re: 360 supercomputers, was Sixteen general registers, 15 index registers [message #384596 is a reply to message #384592] Tue, 25 June 2019 15:01
Quadibloc is currently offline  Quadibloc
Messages: 3552
Registered: June 2012
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Senior Member
On Tuesday, June 25, 2019 at 12:17:15 PM UTC-6, Alan Bowler wrote:

> Isn't that called hyper-threading today?

No! HyperThreading is an Intel trademark. Only Intel processors can ever have
HyperThreading.

Of course, AMD's Ryzen processors do have SMT, Simultaneous Multi-threading, which
is the generic name for the technology.

John Savard
Re: 360 supercomputers, was Sixteen general registers, 15 index registers [message #384597 is a reply to message #384595] Tue, 25 June 2019 15:04
Anonymous
Karma:
Originally posted by: timcaffrey420

On Tuesday, June 25, 2019 at 2:59:43 PM UTC-4, Quadibloc wrote:
> On Tuesday, June 25, 2019 at 12:25:49 PM UTC-6, Scott Lurndal wrote:
>> Alan Bowler <atbowler@thinkage.ca> writes:
>>> On 2019-05-02 1:29 p.m., timcaffrey420@gmail.com wrote:
>>>> (And really, on the CDC 6000 series there was only one PP, it
>>>> was just multiplexed (barrel execution) by 10).
>>>> 4K 12 bit words, 18 bit accumulator.
>>>
>>> Isn't that called hyper-threading today?
>>
>> Not accuratly, no.
>>
>> Hyperthreading simply overprovisions the superscaler nature of the
>> processor pipeline with additional register sets[*] (and internal
>> resources such as fifos and scoreboards) to create the illusion of multiple processors on a
>> single core.
>>
>> [*] Including all (or most) of the privileged registers such
>> as the page table base register &c.
>
> Barrel execution is very similar to simultaneous multiprocessing. Both create
> the illusion of multiple computers on one physical CPU, both require multiple
> sets of registers.
>
> In fact, I would be inclined to say that barrel execution _is_ an example of
> SMP. Not all SMP is barrel execution, however: barrel execution meant that the
> CDC 6600's peripheral processors all ran at 1/10 the speed of the underlying
> hardware even if some of them were idle - so the PP hardware always cycled
> through the 10 virtual PPs in strict succession.
>
> On an Intel processor with Intel Hyperthreading brand SMP, or on a Ryzen with
> SMP, if there is no second thread, the core spends all its time on the first
> one.
>
> Barrel execution, thus, is the simplest and most primitive form of SMP. And, of
> course, as the architecture of the peripheral processor was that of a CDC 1604,
> it didn't have a pipeline, or page tables, to worry about - just an accumulator
> and a carry bit.
>
> John Savard

The PPs were one's complement, there was no carry bit (or interrupts).
- Tim



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