| Apple IIe bus timing [message #354579] |
Tue, 17 October 2017 00:42  |
anthonypaulo
Messages: 531
Registered: September 2013
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I want to make sure I'm reading Sathers' bus timing right (pages 4-7 and 4-8) and would appreciate confirmation or correction :
If I'm a peripheral card and want to write to the Apple II bus :
Place address on Address Bus and set R/W' LOW no more than 124ns after Phase 0 falls and place data on Data Bus no more than 108ns after Phase 0 rises; is this right? If so, how long do I need to keep the data there before it gets latched or 'clocked'?
Thanks in advance,
Anthony
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| Re: Apple IIe bus timing [message #354581 is a reply to message #354579] |
Tue, 17 October 2017 01:41  |
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Originally posted by: Jorge
On Tuesday, October 17, 2017 at 6:43:00 AM UTC+2, Anthony Ortiz wrote:
> I want to make sure I'm reading Sathers' bus timing right (pages 4-7 and 4-8) and would appreciate confirmation or correction :
>
> If I'm a peripheral card and want to write to the Apple II bus :
1.- PULL DOWN /DMA
> Place address on Address Bus and set R/W' LOW no more than 124ns after Phase 0 falls and place data on Data Bus no more than 108ns after Phase 0 rises; is this right? If so, how long do I need to keep the data there before it gets latched or 'clocked'?
Until the falling edge of Ø2 which is ~= Ø0 in the Apple II.
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Jorge.
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| Re: Apple IIe bus timing [message #354592 is a reply to message #354587] |
Tue, 17 October 2017 05:46 |
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Originally posted by: Jorge
Lol, even at this the IIe is worse than the original:
The DMA device must allow 130 ns for the MD IN/OUT line to change, plus the delay for the 74LS245 to change directions which takes 25 ns, for a total of 155 ns.
After this 155 ns, the data must be valid on the bus within 55 ns, because the RAM requires data be setup at the CAS falling edge, which occurs 210 ns into 0o. This does not leave any time to spare, since, for example, a 74LS245 has a 40 ns enable time
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Jorge
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| Re: Apple IIe bus timing [message #354643 is a reply to message #354581] |
Tue, 17 October 2017 20:07 |
anthonypaulo
Messages: 531
Registered: September 2013
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Question: what if, when Phase 0 falls and I place address on address bus and set R/W' to LOW so I can write a byte to RAM, I also place the data on the bus right away and hold it there until a little bit after Phase 0 falls.... will that achieve the same effect? Or is putting data down early mess things up?
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| Re: Apple IIe bus timing [message #354680 is a reply to message #354643] |
Wed, 18 October 2017 11:24 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> Question: what if, when Phase 0 falls and I place address on address bus
> and set R/W' to LOW so I can write a byte to RAM, I also place the data
> on the bus right away and hold it there until a little bit after Phase 0
> falls... will that achieve the same effect? Or is putting data down early mess things up?
>
Extra setup time is usually a good thing, as long as it doesn't extend back
into somebody else's hold time. ;-)
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-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Apple IIe bus timing [message #354710 is a reply to message #354643] |
Wed, 18 October 2017 17:03 |
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Originally posted by: Jorge
On Wednesday, October 18, 2017 at 2:07:15 AM UTC+2, Anthony Ortiz wrote:
> Question: what if, when Phase 0 falls and I place address on address bus and set R/W' to LOW so I can write a byte to RAM, I also place the data on the bus right away and hold it there until a little bit after Phase 0 falls.... will that achieve the same effect? Or is putting data down early mess things up?
You can't drive the data bus except in Ø0, and in the IIe it seems that you must (should?) NOT drive the data bus until after 155ns past the rising edge of Ø0, and then you've got only 55ns to put the data in there or the RAM may fail to grab it properly. The IIe is rubbish in so many uncountable ways...
See the previous message, it's in the tech notes J.Brooks has posted.
Then when Ø0 falls you've got to release it asap, in ns.
--
Jorge.
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| Re: Apple IIe bus timing [message #354744 is a reply to message #354710] |
Thu, 19 October 2017 10:15 |
anthonypaulo
Messages: 531
Registered: September 2013
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Thanks guys, and @John that link you sent was perfect, a 'for dummies' walk through of the dma hardware protocol. I am now able to write to the Apple IIgs although I am experiencing about 5 errors every 10 million writes, but i think I know what the problem is and I just need to tweak a delay. You guys are a wealth of knowledge, thanks again!
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| Re: Apple IIe bus timing [message #354745 is a reply to message #354744] |
Thu, 19 October 2017 10:21 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Speaking of doing this on the IIgs, can I assume that it would work on other Apple II's? The doc you sent states that since the IIe is more sensitive to timing, if it works on the IIe it will work on the other II's; is that also the case for the IIgs?
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