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Emulator instruction heuristics [message #354519] Mon, 16 October 2017 11:46 Go to next message
anthonypaulo is currently offline  anthonypaulo
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Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic
Re: Emulator instruction heuristics [message #354520 is a reply to message #354519] Mon, 16 October 2017 12:01 Go to previous messageGo to next message
mverpelli is currently offline  mverpelli
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On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
> Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic

Some one did

http://www.slack.net/~ant/nes-emu/6502.html#frequent

Marco
Re: Emulator instruction heuristics [message #354521 is a reply to message #354520] Mon, 16 October 2017 12:15 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
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Oh very nice! That's the SNES though, wonder if there would be a big difference on the Apple II platform.
Re: Emulator instruction heuristics [message #354571 is a reply to message #354520] Mon, 16 October 2017 22:36 Go to previous messageGo to next message
gids.rs is currently offline  gids.rs
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On Monday, October 16, 2017 at 10:01:53 AM UTC-6, Marco Verpelli wrote:
> On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
>> Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic
>
> Some one did
>
> http://www.slack.net/~ant/nes-emu/6502.html#frequent
>
> Marco


I pretty much agree with the order of the list except for one. The JSR should be higher in the list. Especially when it comes to calling subroutines at least twice and would save at least five bytes (counting the two JSR absolute addresses and two RTS) compared to having the routine in-line with the code.

This can have a fair substantial savings of memory which would especially be needed on the Apple.
Re: Emulator instruction heuristics [message #354572 is a reply to message #354571] Mon, 16 October 2017 22:45 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
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On Monday, October 16, 2017 at 10:36:04 PM UTC-4, gid...@sasktel.net wrote:
> On Monday, October 16, 2017 at 10:01:53 AM UTC-6, Marco Verpelli wrote:
>> On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
>>> Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic
>>
>> Some one did
>>
>> http://www.slack.net/~ant/nes-emu/6502.html#frequent
>>
>> Marco
>
>
> I pretty much agree with the order of the list except for one. The JSR should be higher in the list. Especially when it comes to calling subroutines at least twice and would save at least five bytes (counting the two JSR absolute addresses and two RTS) compared to having the routine in-line with the code.
>
> This can have a fair substantial savings of memory which would especially be needed on the Apple.

Given that it's a gaming console (SNES) I would expect there to be fewer JSR's than usual as the code is optimized to inline most calls.
Re: Emulator instruction heuristics [message #354585 is a reply to message #354572] Tue, 17 October 2017 02:26 Go to previous messageGo to next message
mverpelli is currently offline  mverpelli
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On Tuesday, October 17, 2017 at 4:45:51 AM UTC+2, Anthony Ortiz wrote:
> On Monday, October 16, 2017 at 10:36:04 PM UTC-4, gid...@sasktel.net wrote:
>> On Monday, October 16, 2017 at 10:01:53 AM UTC-6, Marco Verpelli wrote:
>>> On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
>>>> Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic
>>>
>>> Some one did
>>>
>>> http://www.slack.net/~ant/nes-emu/6502.html#frequent
>>>
>>> Marco
>>
>>
>> I pretty much agree with the order of the list except for one. The JSR should be higher in the list. Especially when it comes to calling subroutines at least twice and would save at least five bytes (counting the two JSR absolute addresses and two RTS) compared to having the routine in-line with the code.
>>
>> This can have a fair substantial savings of memory which would especially be needed on the Apple.
>
> Given that it's a gaming console (SNES) I would expect there to be fewer JSR's than usual as the code is optimized to inline most calls.

What amazes me is the absence of push/pop opcodes

Marco
Re: Emulator instruction heuristics [message #354604 is a reply to message #354572] Tue, 17 October 2017 10:35 Go to previous messageGo to next message
gids.rs is currently offline  gids.rs
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On Monday, October 16, 2017 at 8:45:51 PM UTC-6, Anthony Ortiz wrote:
> On Monday, October 16, 2017 at 10:36:04 PM UTC-4, gid...@sasktel.net wrote:
>> On Monday, October 16, 2017 at 10:01:53 AM UTC-6, Marco Verpelli wrote:
>>> On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
>>>> Has anyone gathered any instruction heuristics in the emulators? It would be interesting to see how often certain instructions are used in order to optimize the instruction branch/jump table logic
>>>
>>> Some one did
>>>
>>> http://www.slack.net/~ant/nes-emu/6502.html#frequent
>>>
>>> Marco
>>
>>
>> I pretty much agree with the order of the list except for one. The JSR should be higher in the list. Especially when it comes to calling subroutines at least twice and would save at least five bytes (counting the two JSR absolute addresses and two RTS) compared to having the routine in-line with the code.
>>
>> This can have a fair substantial savings of memory which would especially be needed on the Apple.
>
> Given that it's a gaming console (SNES) I would expect there to be fewer JSR's than usual as the code is optimized to inline most calls.


Yeh, so for the Apple the JSR and the JMP probably could be switched around..
Re: Emulator instruction heuristics [message #354658 is a reply to message #354520] Wed, 18 October 2017 03:27 Go to previous messageGo to next message
Michael J. Mahon is currently offline  Michael J. Mahon
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Marco Verpelli <mverpelli@libero.it> wrote:
> On Monday, October 16, 2017 at 5:46:41 PM UTC+2, Anthony Ortiz wrote:
>> Has anyone gathered any instruction heuristics in the emulators? It
>> would be interesting to see how often certain instructions are used in
>> order to optimize the instruction branch/jump table logic
>
> Some one did
>
> http://www.slack.net/~ant/nes-emu/6502.html#frequent
>
> Marco
>

As usual, the frequency distribution depends on the workload, so for an
emulator, you'd like a pretty diverse workload, with each program's results
weighted by that program's expected usage in the emulator.

This would be a very interesting set of frequencies. I've been curious
about it for a long time, but have never measured it. An emulator is a very
convenient vehicle for doing so.

--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Re: Emulator instruction heuristics [message #354659 is a reply to message #354658] Wed, 18 October 2017 06:54 Go to previous messageGo to next message
sicklittlemonkey is currently offline  sicklittlemonkey
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On Wednesday, 18 October 2017 20:28:04 UTC+13, Michael J. Mahon wrote:
> An emulator is a very vehicle for doing so.

Indeed. ; - )

Here is the Top 20 instruction profile for Robotron:

34.42% D0 BNE $addr
33.17% 88 DEY
2.38% 91 STA ($00),Y
2.30% 85 STA $00
2.22% C8 INY
2.14% 10 BPL $addr
1.80% B1 LDA ($00),Y
1.53% F0 BEQ $addr
1.51% A5 LDA $00
1.50% 20 JSR $1100
1.49% 60 RTS
1.43% 90 BCC $addr
1.15% CA DEX
1.13% AD LDA $1100
1.06% E6 INC $00
1.04% 65 ADC $00
0.89% A1 LDA ($00,X)
0.82% A4 LDY $00
0.78% 49 EOR #$00
0.76% BD LDA $1100,X

Cheers,
Nick.
Re: Emulator instruction heuristics [message #354661 is a reply to message #354571] Wed, 18 October 2017 08:37 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
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It really depends on the application.

This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.

ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf

Here's the top 33 opcodes, and assembler directives -- pity that they didn't filter out all the assembler directives

# Opcode Name Freq Histogram
000248 --- ------------ ----- ----------------------------------------
000249 [ 1] LDA 1864 ****************************************
000250 [ 2] STA 1406 *******************************
000251 [ 3] EQU 1134 *************************
000252 [ 4] JSR 546 *************
000253 [ 5] LDY 450 ***********
000254 [ 6] REP 417 **********
000255 [ 7] BNE 397 **********
000256 [ 8] RTS 324 ********
000257 [ 9] BEQ 291 ********
000258 [ 10] CMP 286 *******
000259 [ 11] BCS 274 *******
000260 [ 12] LDX 266 *******
000261 [ 13] PAGE 246 *******
000262 [ 14] EXTRN 242 *******
000263 [ 15] BCC 240 *******
000264 [ 16] DS 210 ******
000265 [ 17] JMP 199 ******
000266 [ 18] ENTRY 190 *****
000267 [ 19] DFB 188 *****
000268 [ 20] CLC 181 *****
000269 [ 21] AND 147 *****
000270 [ 22] INY 143 ****
000271 [ 23] SEC 136 ****
000272 [ 24] INC 131 ****
000273 [ 25] DEY 126 ****
000274 [ 26] ADC 125 ****
000275 [ 27] BPL 121 ****
000276 [ 28] SBC 111 ****
000277 [ 29] ORA 100 ****
000278 [ 30] LSR 93 ***
000279 [ 31] TAX 93 ***
000280 [ 32] PLA 91 ***
000281 [ 33] PHA 90 ***
000282 [ 34] STX 84 ***
Re: Emulator instruction heuristics [message #354676 is a reply to message #354661] Wed, 18 October 2017 09:42 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
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On Wednesday, October 18, 2017 at 8:37:14 AM UTC-4, Michael AppleWin Debugger Dev wrote:
> It really depends on the application.
>
> This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.
>
> ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf
>
> Here's the top 33 opcodes, and assembler directives -- pity that they didn't filter out all the assembler directives
>
> # Opcode Name Freq Histogram
> 000248 --- ------------ ----- ----------------------------------------
> 000249 [ 1] LDA 1864 ****************************************
> 000250 [ 2] STA 1406 *******************************
> 000251 [ 3] EQU 1134 *************************
> 000252 [ 4] JSR 546 *************
> 000253 [ 5] LDY 450 ***********
> 000254 [ 6] REP 417 **********
> 000255 [ 7] BNE 397 **********
> 000256 [ 8] RTS 324 ********
> 000257 [ 9] BEQ 291 ********
> 000258 [ 10] CMP 286 *******
> 000259 [ 11] BCS 274 *******
> 000260 [ 12] LDX 266 *******
> 000261 [ 13] PAGE 246 *******
> 000262 [ 14] EXTRN 242 *******
> 000263 [ 15] BCC 240 *******
> 000264 [ 16] DS 210 ******
> 000265 [ 17] JMP 199 ******
> 000266 [ 18] ENTRY 190 *****
> 000267 [ 19] DFB 188 *****
> 000268 [ 20] CLC 181 *****
> 000269 [ 21] AND 147 *****
> 000270 [ 22] INY 143 ****
> 000271 [ 23] SEC 136 ****
> 000272 [ 24] INC 131 ****
> 000273 [ 25] DEY 126 ****
> 000274 [ 26] ADC 125 ****
> 000275 [ 27] BPL 121 ****
> 000276 [ 28] SBC 111 ****
> 000277 [ 29] ORA 100 ****
> 000278 [ 30] LSR 93 ***
> 000279 [ 31] TAX 93 ***
> 000280 [ 32] PLA 91 ***
> 000281 [ 33] PHA 90 ***
> 000282 [ 34] STX 84 ***

They listed the frequency of opcodes in their source code but not the actual frequency of execution. I wonder why they bothered listing this in their source; I don't see how it would have been useful.
Re: Emulator instruction heuristics [message #354677 is a reply to message #354676] Wed, 18 October 2017 10:04 Go to previous messageGo to next message
David Schmidt is currently offline  David Schmidt
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On 10/18/2017 9:42 AM, Anthony Ortiz wrote:
> They listed the frequency of opcodes in their source code but not the actual frequency of execution. I wonder why they bothered listing this in their source; I don't see how it would have been useful.

It wasn't useful. It was just available and countable during the
process of assembly, so the assembler spat it out. About the only
situation where static analysis like this would be useful would be for
CPU (or maybe assembler) testing - ensuring you had full "code"
coverage. But this thread is all about dynamic analysis - actual use in
running code.
Re: Emulator instruction heuristics [message #354678 is a reply to message #354661] Wed, 18 October 2017 10:16 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
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On Wednesday, October 18, 2017 at 8:37:14 AM UTC-4, Michael AppleWin Debugger Dev wrote:
> It really depends on the application.
>
> This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.
>
> ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf
>
> Here's the top 33 opcodes, and assembler directives -- pity that they didn't filter out all the assembler directives
>
> # Opcode Name Freq Histogram
> 000248 --- ------------ ----- ----------------------------------------
> 000249 [ 1] LDA 1864 ****************************************
> 000250 [ 2] STA 1406 *******************************
> 000251 [ 3] EQU 1134 *************************
> 000252 [ 4] JSR 546 *************
> 000253 [ 5] LDY 450 ***********
> 000254 [ 6] REP 417 **********
> 000255 [ 7] BNE 397 **********
> 000256 [ 8] RTS 324 ********
> 000257 [ 9] BEQ 291 ********
> 000258 [ 10] CMP 286 *******
> 000259 [ 11] BCS 274 *******
> 000260 [ 12] LDX 266 *******
> 000261 [ 13] PAGE 246 *******
> 000262 [ 14] EXTRN 242 *******
> 000263 [ 15] BCC 240 *******
> 000264 [ 16] DS 210 ******
> 000265 [ 17] JMP 199 ******
> 000266 [ 18] ENTRY 190 *****
> 000267 [ 19] DFB 188 *****
> 000268 [ 20] CLC 181 *****
> 000269 [ 21] AND 147 *****
> 000270 [ 22] INY 143 ****
> 000271 [ 23] SEC 136 ****
> 000272 [ 24] INC 131 ****
> 000273 [ 25] DEY 126 ****
> 000274 [ 26] ADC 125 ****
> 000275 [ 27] BPL 121 ****
> 000276 [ 28] SBC 111 ****
> 000277 [ 29] ORA 100 ****
> 000278 [ 30] LSR 93 ***
> 000279 [ 31] TAX 93 ***
> 000280 [ 32] PLA 91 ***
> 000281 [ 33] PHA 90 ***
> 000282 [ 34] STX 84 ***

@Michael, are there any facilities in AppleWin for collecting and generating frequency of execution?
Re: Emulator instruction heuristics [message #354679 is a reply to message #354661] Wed, 18 October 2017 10:17 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
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@Michael, are there any facilities in AppleWin for collecting and generating frequency of execution?
Re: Emulator instruction heuristics [message #354683 is a reply to message #354661] Wed, 18 October 2017 11:32 Go to previous messageGo to next message
Michael J. Mahon is currently offline  Michael J. Mahon
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Michael AppleWin Debugger Dev <michael.pohoreski@gmail.com> wrote:
> It really depends on the application.
>
> This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.
>
> ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf
>
> Here's the top 33 opcodes, and assembler directives -- pity that they
> didn't filter out all the assembler directives
>
> # Opcode Name Freq Histogram
> 000248 --- ------------ ----- ----------------------------------------
> 000249 [ 1] LDA 1864 ****************************************
> 000250 [ 2] STA 1406 *******************************
> 000251 [ 3] EQU 1134 *************************
> 000252 [ 4] JSR 546 *************
> 000253 [ 5] LDY 450 ***********
> 000254 [ 6] REP 417 **********
> 000255 [ 7] BNE 397 **********
> 000256 [ 8] RTS 324 ********
> 000257 [ 9] BEQ 291 ********
> 000258 [ 10] CMP 286 *******
> 000259 [ 11] BCS 274 *******
> 000260 [ 12] LDX 266 *******
> 000261 [ 13] PAGE 246 *******
> 000262 [ 14] EXTRN 242 *******
> 000263 [ 15] BCC 240 *******
> 000264 [ 16] DS 210 ******
> 000265 [ 17] JMP 199 ******
> 000266 [ 18] ENTRY 190 *****
> 000267 [ 19] DFB 188 *****
> 000268 [ 20] CLC 181 *****
> 000269 [ 21] AND 147 *****
> 000270 [ 22] INY 143 ****
> 000271 [ 23] SEC 136 ****
> 000272 [ 24] INC 131 ****
> 000273 [ 25] DEY 126 ****
> 000274 [ 26] ADC 125 ****
> 000275 [ 27] BPL 121 ****
> 000276 [ 28] SBC 111 ****
> 000277 [ 29] ORA 100 ****
> 000278 [ 30] LSR 93 ***
> 000279 [ 31] TAX 93 ***
> 000280 [ 32] PLA 91 ***
> 000281 [ 33] PHA 90 ***
> 000282 [ 34] STX 84 ***
>

Static frequencies are not representative of dynamic frequencies, and
dynamic frequencies are distorted in practice by "wait loops", for which
performance is not an issue.

--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Re: Emulator instruction heuristics [message #354684 is a reply to message #354676] Wed, 18 October 2017 11:32 Go to previous messageGo to next message
Michael J. Mahon is currently offline  Michael J. Mahon
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> On Wednesday, October 18, 2017 at 8:37:14 AM UTC-4, Michael AppleWin Debugger Dev wrote:
>> It really depends on the application.
>>
>> This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.
>>
>> ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf
>>
>> Here's the top 33 opcodes, and assembler directives -- pity that they
>> didn't filter out all the assembler directives
>>
>> # Opcode Name Freq Histogram
>> 000248 --- ------------ ----- ----------------------------------------
>> 000249 [ 1] LDA 1864 ****************************************
>> 000250 [ 2] STA 1406 *******************************
>> 000251 [ 3] EQU 1134 *************************
>> 000252 [ 4] JSR 546 *************
>> 000253 [ 5] LDY 450 ***********
>> 000254 [ 6] REP 417 **********
>> 000255 [ 7] BNE 397 **********
>> 000256 [ 8] RTS 324 ********
>> 000257 [ 9] BEQ 291 ********
>> 000258 [ 10] CMP 286 *******
>> 000259 [ 11] BCS 274 *******
>> 000260 [ 12] LDX 266 *******
>> 000261 [ 13] PAGE 246 *******
>> 000262 [ 14] EXTRN 242 *******
>> 000263 [ 15] BCC 240 *******
>> 000264 [ 16] DS 210 ******
>> 000265 [ 17] JMP 199 ******
>> 000266 [ 18] ENTRY 190 *****
>> 000267 [ 19] DFB 188 *****
>> 000268 [ 20] CLC 181 *****
>> 000269 [ 21] AND 147 *****
>> 000270 [ 22] INY 143 ****
>> 000271 [ 23] SEC 136 ****
>> 000272 [ 24] INC 131 ****
>> 000273 [ 25] DEY 126 ****
>> 000274 [ 26] ADC 125 ****
>> 000275 [ 27] BPL 121 ****
>> 000276 [ 28] SBC 111 ****
>> 000277 [ 29] ORA 100 ****
>> 000278 [ 30] LSR 93 ***
>> 000279 [ 31] TAX 93 ***
>> 000280 [ 32] PLA 91 ***
>> 000281 [ 33] PHA 90 ***
>> 000282 [ 34] STX 84 ***
>
> They listed the frequency of opcodes in their source code but not the
> actual frequency of execution. I wonder why they bothered listing this in
> their source; I don't see how it would have been useful.
>

No doubt, it was provided by the assembler they used...

--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Re: Emulator instruction heuristics [message #354685 is a reply to message #354661] Wed, 18 October 2017 11:32 Go to previous messageGo to next message
Michael J. Mahon is currently offline  Michael J. Mahon
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Michael AppleWin Debugger Dev <michael.pohoreski@gmail.com> wrote:
> It really depends on the application.
>
> This source code for Apple's SOS on page 10 has all the opcodes sorted by frequency.
>
> ftp://ftp.apple.asimov.net/pub/apple_II/documentation/apple3 /dtca3doc/DTCA3DOC-180B%20apple%203%20sos%2013%20source%20li sting.pdf
>
> Here's the top 33 opcodes, and assembler directives -- pity that they
> didn't filter out all the assembler directives
>
> # Opcode Name Freq Histogram
> 000248 --- ------------ ----- ----------------------------------------
> 000249 [ 1] LDA 1864 ****************************************
> 000250 [ 2] STA 1406 *******************************
> 000251 [ 3] EQU 1134 *************************
> 000252 [ 4] JSR 546 *************
> 000253 [ 5] LDY 450 ***********
> 000254 [ 6] REP 417 **********
> 000255 [ 7] BNE 397 **********
> 000256 [ 8] RTS 324 ********
> 000257 [ 9] BEQ 291 ********
> 000258 [ 10] CMP 286 *******
> 000259 [ 11] BCS 274 *******
> 000260 [ 12] LDX 266 *******
> 000261 [ 13] PAGE 246 *******
> 000262 [ 14] EXTRN 242 *******
> 000263 [ 15] BCC 240 *******
> 000264 [ 16] DS 210 ******
> 000265 [ 17] JMP 199 ******
> 000266 [ 18] ENTRY 190 *****
> 000267 [ 19] DFB 188 *****
> 000268 [ 20] CLC 181 *****
> 000269 [ 21] AND 147 *****
> 000270 [ 22] INY 143 ****
> 000271 [ 23] SEC 136 ****
> 000272 [ 24] INC 131 ****
> 000273 [ 25] DEY 126 ****
> 000274 [ 26] ADC 125 ****
> 000275 [ 27] BPL 121 ****
> 000276 [ 28] SBC 111 ****
> 000277 [ 29] ORA 100 ****
> 000278 [ 30] LSR 93 ***
> 000279 [ 31] TAX 93 ***
> 000280 [ 32] PLA 91 ***
> 000281 [ 33] PHA 90 ***
> 000282 [ 34] STX 84 ***
>

Static frequencies are not representative of dynamic frequencies, and
dynamic frequencies are distorted in practice by "wait loops", for which
performance is not an issue.

--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Re: Emulator instruction heuristics [message #354686 is a reply to message #354678] Wed, 18 October 2017 11:32 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
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Yes, use the debugger PROFILE command. i.e. HELP PROFILE

I guess the help should be updated to include these steps.

1. F7
2. PROFILE RESET
3. G
4. ... exec your commands ...
5. F7
6. PROFILE LIST
7. PROFILE SAVE
Re: Emulator instruction heuristics [message #354687 is a reply to message #354677] Wed, 18 October 2017 11:35 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
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Yeah, I agree David. While the static analysis metrics are "interesting" from a theoretical POV, from a practical POV they are mostly useless.

Dynamic analysis is what everyone cares about. i.e. JIT, Dynamic Virtual CPU Instructions, etc.
Re: Emulator instruction heuristics [message #354688 is a reply to message #354679] Wed, 18 October 2017 11:45 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
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Here is an practical example:

F7
BPX HGR
G
PROFILE RESET
RTS
PROFILE LIST
PROFILE SAVE

Annoyingly, the file "Profile.txt" is saved in the directory of AppleWin.exe -- and NOT the current debugger directory (PWD). Probably should log a bug for that but I digress.

Here is a snippet:

"Percent" "Count" "Opcode" "Mnemonic" "Addressing Mode"
11.1346% 8225 "A5" LDA "Zero Page"
11.1332% 8224 "D0" BNE "Relative"
11.0913% 8193 "60" RTS "(implied)"
11.0899% 8192 "20" JSR "Absolute"
11.0899% 8192 "0A" ASL "(implied)"
11.0899% 8192 "10" BPL "Relative"
11.0899% 8192 "91" STA "(Zero Page),Y"
11.0899% 8192 "C8" INY "(implied)"
11.0899% 8192 "C9" CMP "Immediate"
0.0433% 32 "29" AND "Immediate"
0.0433% 32 "E6" INC "Zero Page"
0.0041% 3 "85" STA "Zero Page"
0.0027% 2 "2C" BIT "Absolute"
0.0027% 2 "A9" LDA "Immediate"
0.0027% 2 "AD" LDA "Absolute"
0.0014% 1 "A0" LDY "Immediate"
0.0014% 1 "84" STY "Zero Page"
Total: 73869

"Percent" "Count" "Addressing Mode"
33.2711% 24577 "(implied)"
22.2231% 16416 "Relative"
11.1833% 8261 "Zero Page"
11.1373% 8227 "Immediate"
11.0953% 8196 "Absolute"
11.0899% 8192 "(Zero Page),Y"
Total: 73869

Cheers
Re: Emulator instruction heuristics [message #354689 is a reply to message #354688] Wed, 18 October 2017 11:50 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
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Registered: March 2013
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Senior Member
Whoops, missed a crucial step. :-) Those instructions should be:

F7
BPX HGR
G
HGR
PROFILE RESET
RTS
PROFILE LIST
PROFILE SAVE
Re: Emulator instruction heuristics [message #354690 is a reply to message #354686] Wed, 18 October 2017 12:02 Go to previous messageGo to next message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
Messages: 1262
Registered: March 2013
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Senior Member
Also of interest is the debugger Trace File command: TF

F7
BPX HGR
G
HGR
BPX f410
TF "trace_hgr.txt"
G
.... wait 10 secs... because tracing is D-O-G slow ...
TF

This will dump a 3.6 MB "time line" of every instruction executed.
Here is a snippet ...

A: X: Y: SP: Flags Addr:Opcode Mnemonic
00 00 22 01F6 ..RB.IZC F3E2:A9 20 LDA #$20
20 00 22 01F6 ..RB.I.C F3E4:2C 54 C0 BIT $C054
20 00 22 01F6 ..RB.IZC F3E7:2C 53 C0 BIT $C053
20 00 22 01F6 ..RB.IZC F3EA:85 E6 STA $E6

I guess a new category "Profiling", "Metrics" or "Performance" would be handy.

Cheers,
Michael
Re: Emulator instruction heuristics [message #354691 is a reply to message #354690] Wed, 18 October 2017 12:06 Go to previous messageGo to next message
anthonypaulo is currently offline  anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
Senior Member
On Wednesday, October 18, 2017 at 12:02:45 PM UTC-4, Michael AppleWin Debugger Dev wrote:
> Also of interest is the debugger Trace File command: TF
>
> F7
> BPX HGR
> G
> HGR
> BPX f410
> TF "trace_hgr.txt"
> G
> ... wait 10 secs... because tracing is D-O-G slow ...
> TF
>
> This will dump a 3.6 MB "time line" of every instruction executed.
> Here is a snippet ...
>
> A: X: Y: SP: Flags Addr:Opcode Mnemonic
> 00 00 22 01F6 ..RB.IZC F3E2:A9 20 LDA #$20
> 20 00 22 01F6 ..RB.I.C F3E4:2C 54 C0 BIT $C054
> 20 00 22 01F6 ..RB.IZC F3E7:2C 53 C0 BIT $C053
> 20 00 22 01F6 ..RB.IZC F3EA:85 E6 STA $E6
>
> I guess a new category "Profiling", "Metrics" or "Performance" would be handy.
>
> Cheers,
> Michael

Michael is BAWS!
Re: Emulator instruction heuristics [message #354952 is a reply to message #354691] Fri, 20 October 2017 13:05 Go to previous message
Michael AppleWin Debu is currently offline  Michael AppleWin Debu
Messages: 1262
Registered: March 2013
Karma: 0
Senior Member
I'm just a geek interested in (some of) the same stuff as you. ;-)
That's why I added the PROFILE command in the first place years ago.
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