| Apple II bus cycles when the ZipChip is running off cache [message #354450] |
Sun, 15 October 2017 08:57  |
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Originally posted by: Jorge
Hi,
Any idea what does the Zipchip do with the apple II bus when it's running code that's 100% in its cache?
For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM that code runs 100% off the cache, but the MLB cycles continue... what does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
Any ideas?
--
Jorge.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354451 is a reply to message #354450] |
Sun, 15 October 2017 09:44  |
STYNX
Messages: 453
Registered: October 2012
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 2:57:34 PM UTC+2, Jorge wrote:
> Hi,
>
> Any idea what does the Zipchip do with the apple II bus when it's running code that's 100% in its cache?
>
> For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM that code runs 100% off the cache, but the MLB cycles continue... what does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
>
> Any ideas?
>
> --
> Jorge.
Any write to a memory location is synchronized with the Apple II memory. This is accomplished by the ZIP-ASIC and may even be buffered (but I doubt that). Sadly the ZIP-Chip ASIC has not been analyzed yet. Here are high resolution DIE shots: https://drive.google.com/open?id=0B5SAWSGa49rLamJSZTloVkphQj A
-Jonas
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354458 is a reply to message #354451] |
Sun, 15 October 2017 12:21 |
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Originally posted by: James Davis
On Sunday, October 15, 2017 at 6:44:07 AM UTC-7, STYNX wrote:
> On Sunday, October 15, 2017 at 2:57:34 PM UTC+2, Jorge wrote:
>> Hi,
>>
>> Any idea what does the Zipchip do with the apple II bus when it's running code that's 100% in its cache?
>>
>> For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM that code runs 100% off the cache, but the MLB cycles continue... what does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
>>
>> Any ideas?
>>
>> --
>> Jorge.
>
> Any write to a memory location is synchronized with the Apple II memory. This is accomplished by the ZIP-ASIC and may even be buffered (but I doubt that). Sadly the ZIP-Chip ASIC has not been analyzed yet. Here are high resolution DIE shots: https://drive.google.com/open?id=0B5SAWSGa49rLamJSZTloVkphQj A
>
> -Jonas
Sounds like a job for Carte Blanche (I or II) People.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354461 is a reply to message #354450] |
Sun, 15 October 2017 12:42 |
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Originally posted by: R.Kiefer.SPAEM
Jorge wrote:
> For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM
> that code runs 100% off the cache, but the MLB cycles continue... what
> does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
I guess: nothing which is useful for the code running on the fast CPU.
And nothing which affects any I/O.
The MLB and BE signals from the 65C02 are not available with the NMOS
6502. Means the Apple mainboard doesn't use these signals.
But the ZipChip must drive the address bus, R/W, PHI1 and PHI2.
Regards, Ralf
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354473 is a reply to message #354461] |
Sun, 15 October 2017 16:00 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 12:42:05 PM UTC-4, Ralf Kiefer wrote:
> Jorge wrote:
>
>> For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM
>> that code runs 100% off the cache, but the MLB cycles continue... what
>> does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
>
> I guess: nothing which is useful for the code running on the fast CPU.
> And nothing which affects any I/O.
>
> The MLB and BE signals from the 65C02 are not available with the NMOS
> 6502. Means the Apple mainboard doesn't use these signals.
>
> But the ZipChip must drive the address bus, R/W, PHI1 and PHI2.
>
> Regards, Ralf
Why PH1 and PH2? I think the ZipChip can do without driving those lines since they're not used.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354476 is a reply to message #354474] |
Sun, 15 October 2017 19:01 |
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Originally posted by: Jorge
On Sunday, October 15, 2017 at 10:20:01 PM UTC+2, Ralf Kiefer wrote:
> Anthony Ortiz wrote:
>
>> Why PH1 and PH2? I think the ZipChip can do without driving those lines
>> since they're not used.
>
> Sorry, you're right.
>
In my Apple II *that* Ø1 is what gates the data bus transceivers on every write cycle, so... used it is used. Only that when R/W is high Ø1 is a don't care from the point of view of the bus transceivers.
That it puts R/W high (while running a `loop jmp loop` off its cache) is almost sure, and stop (or not) Ø1 because it's a don't care is a possibility.
What else? E.g. what address(es?) does it put/leave on the address bus? Anybody knows?
--
Jorge.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354477 is a reply to message #354476] |
Sun, 15 October 2017 20:20 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 7:01:38 PM UTC-4, Jorge wrote:
> On Sunday, October 15, 2017 at 10:20:01 PM UTC+2, Ralf Kiefer wrote:
>> Anthony Ortiz wrote:
>>
>>> Why PH1 and PH2? I think the ZipChip can do without driving those lines
>>> since they're not used.
>>
>> Sorry, you're right.
>>
>
> In my Apple II *that* Ø1 is what gates the data bus transceivers on every write cycle, so... used it is used. Only that when R/W is high Ø1 is a don't care from the point of view of the bus transceivers.
>
> That it puts R/W high (while running a `loop jmp loop` off its cache) is almost sure, and stop (or not) Ø1 because it's a don't care is a possibility.
>
> What else? E.g. what address(es?) does it put/leave on the address bus? Anybody knows?
>
> --
> Jorge.
Are you talking about the Apple II Phase 1 or the 6502 Phase 1? Because from what I understand the 6502 generated Phase 1 and Phase 2 are never used and the outputs aren't even connected to anything.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354479 is a reply to message #354477] |
Sun, 15 October 2017 20:46 |
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Originally posted by: James Davis
On Sunday, October 15, 2017 at 5:20:11 PM UTC-7, Anthony Ortiz wrote:
> On Sunday, October 15, 2017 at 7:01:38 PM UTC-4, Jorge wrote:
>> On Sunday, October 15, 2017 at 10:20:01 PM UTC+2, Ralf Kiefer wrote:
>>> Anthony Ortiz wrote:
>>>
>>>> Why PH1 and PH2? I think the ZipChip can do without driving those lines
>>>> since they're not used.
>>>
>>> Sorry, you're right.
>>>
>>
>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every write cycle, so... used it is used. Only that when R/W is high Ø1 is a don't care from the point of view of the bus transceivers.
>>
>> That it puts R/W high (while running a `loop jmp loop` off its cache) is almost sure, and stop (or not) Ø1 because it's a don't care is a possibility.
>>
>> What else? E.g. what address(es?) does it put/leave on the address bus? Anybody knows?
>>
>> --
>> Jorge.
>
> Are you talking about the Apple II Phase 1 or the 6502 Phase 1? Because from what I understand the 6502 generated Phase 1 and Phase 2 are never used and the outputs aren't even connected to anything.
Looking at the Apple II schematics, it looks like the phases come from the crystal timing circuitry and go out to whatever needs it. The phases at the 6502 are also connected to things. Phase-0' has an arrow into the microprocessor and phase-1 does not.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354480 is a reply to message #354479] |
Sun, 15 October 2017 20:50 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 8:47:09 PM UTC-4, James Davis wrote:
> On Sunday, October 15, 2017 at 5:20:11 PM UTC-7, Anthony Ortiz wrote:
>> On Sunday, October 15, 2017 at 7:01:38 PM UTC-4, Jorge wrote:
>>> On Sunday, October 15, 2017 at 10:20:01 PM UTC+2, Ralf Kiefer wrote:
>>>> Anthony Ortiz wrote:
>>>>
>>>> > Why PH1 and PH2? I think the ZipChip can do without driving those lines
>>>> >since they're not used.
>>>>
>>>> Sorry, you're right.
>>>>
>>>
>>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every write cycle, so... used it is used. Only that when R/W is high Ø1 is a don't care from the point of view of the bus transceivers.
>>>
>>> That it puts R/W high (while running a `loop jmp loop` off its cache) is almost sure, and stop (or not) Ø1 because it's a don't care is a possibility.
>>>
>>> What else? E.g. what address(es?) does it put/leave on the address bus? Anybody knows?
>>>
>>> --
>>> Jorge.
>>
>> Are you talking about the Apple II Phase 1 or the 6502 Phase 1? Because from what I understand the 6502 generated Phase 1 and Phase 2 are never used and the outputs aren't even connected to anything.
>
> Looking at the Apple II schematics, it looks like the phases come from the crystal timing circuitry and go out to whatever needs it. The phases at the 6502 are also connected to things. Phase-0' has an arrow into the microprocessor and phase-1 does not.
Phase 0 is what drives the 6502, so it will have an arrow going into it. The Phase 1 and Phase 2 clocks, however, are generated inside the 6502 and both Phase 1 and Phase 2 outputs are not connected to anything.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354482 is a reply to message #354476] |
Sun, 15 October 2017 21:09 |
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Originally posted by: R.Kiefer.SPAEM
Jorge wrote:
> In my Apple II *that* Ø1 is what gates the data bus transceivers on every
> write cycle, so... used it is used. Only that when R/W is high Ø1 is a
> don't care from the point of view of the bus transceivers.
In the IIe and IIc PHASE1 (pin 3) and PHASE2 (pin 39) are not connected.
See Jim Sather, Understanding the Apple _IIe_, page 4.2.
But Jim Sather also wrote in Understanding the Apple _II_, page 4.2:
"PHASE2 is not connected in the Apple. PHASE1 is used to control the
direction of the data flow in the external MPU data bus transceivers
during MPU write cycle."
> That it puts R/W high (while running a `loop jmp loop` off its cache) is
> almost sure, and stop (or not) Ø1 because it's a don't care is a
> possibility.
Yes, R/W must be high, means reading from the external bus. But I don't
know the state of the 6502 address bus in case of no bus cyle. If these
even exist ...
Regards, Ralf
with poor quality of my copy of the Apple II schematics
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354483 is a reply to message #354480] |
Sun, 15 October 2017 21:14 |
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Originally posted by: James Davis
On Sunday, October 15, 2017 at 5:51:00 PM UTC-7, Anthony Ortiz wrote:
> On Sunday, October 15, 2017 at 8:47:09 PM UTC-4, James Davis wrote:
>> On Sunday, October 15, 2017 at 5:20:11 PM UTC-7, Anthony Ortiz wrote:
>>> On Sunday, October 15, 2017 at 7:01:38 PM UTC-4, Jorge wrote:
>>>> On Sunday, October 15, 2017 at 10:20:01 PM UTC+2, Ralf Kiefer wrote:
>>>> > Anthony Ortiz wrote:
>>>> >
>>>> > > Why PH1 and PH2? I think the ZipChip can do without driving those lines
>>>> > >since they're not used.
>>>> >
>>>> > Sorry, you're right.
>>>> >
>>>>
>>>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every write cycle, so... used it is used. Only that when R/W is high Ø1 is a don't care from the point of view of the bus transceivers.
>>>>
>>>> That it puts R/W high (while running a `loop jmp loop` off its cache) is almost sure, and stop (or not) Ø1 because it's a don't care is a possibility.
>>>>
>>>> What else? E.g. what address(es?) does it put/leave on the address bus? Anybody knows?
>>>>
>>>> --
>>>> Jorge.
>>>
>>> Are you talking about the Apple II Phase 1 or the 6502 Phase 1? Because from what I understand the 6502 generated Phase 1 and Phase 2 are never used and the outputs aren't even connected to anything.
>>
>> Looking at the Apple II schematics, it looks like the phases come from the crystal timing circuitry and go out to whatever needs it. The phases at the 6502 are also connected to things. Phase-0' has an arrow into the microprocessor and phase-1 does not.
>
> Phase 0 is what drives the 6502, so it will have an arrow going into it. The Phase 1 and Phase 2 clocks, however, are generated inside the 6502 and both Phase 1 and Phase 2 outputs are not connected to anything.
On my schematic, phase-2 is not shown, so it is not connected to anything, but phase-1 goes from the 6502 to 1/4 of 74LS32-C14 and from there is gated to pin-11 of 8304-H10, so it is connected to something.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354484 is a reply to message #354482] |
Sun, 15 October 2017 21:15 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 9:09:32 PM UTC-4, Ralf Kiefer wrote:
> Jorge wrote:
>
>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every
>> write cycle, so... used it is used. Only that when R/W is high Ø1 is a
>> don't care from the point of view of the bus transceivers.
>
> In the IIe and IIc PHASE1 (pin 3) and PHASE2 (pin 39) are not connected.
> See Jim Sather, Understanding the Apple _IIe_, page 4.2.
>
> But Jim Sather also wrote in Understanding the Apple _II_, page 4.2:
> "PHASE2 is not connected in the Apple. PHASE1 is used to control the
> direction of the data flow in the external MPU data bus transceivers
> during MPU write cycle."
>
>
>> That it puts R/W high (while running a `loop jmp loop` off its cache) is
>> almost sure, and stop (or not) Ø1 because it's a don't care is a
>> possibility.
>
> Yes, R/W must be high, means reading from the external bus. But I don't
> know the state of the 6502 address bus in case of no bus cyle. If these
> even exist ...
>
>
> Regards, Ralf
> with poor quality of my copy of the Apple II schematics
My apologies, I should have specified that I was referring to the IIe (as per Sathers). So Phase 1 on the Apple II/II+ controls the databus direction?
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354485 is a reply to message #354482] |
Sun, 15 October 2017 21:18 |
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Originally posted by: James Davis
On Sunday, October 15, 2017 at 6:09:32 PM UTC-7, Ralf Kiefer wrote:
> Jorge wrote:
>
>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every
>> write cycle, so... used it is used. Only that when R/W is high Ø1 is a
>> don't care from the point of view of the bus transceivers.
>
> In the IIe and IIc PHASE1 (pin 3) and PHASE2 (pin 39) are not connected.
> See Jim Sather, Understanding the Apple _IIe_, page 4.2.
>
> But Jim Sather also wrote in Understanding the Apple _II_, page 4.2:
> "PHASE2 is not connected in the Apple. PHASE1 is used to control the
> direction of the data flow in the external MPU data bus transceivers
> during MPU write cycle."
>
>
>> That it puts R/W high (while running a `loop jmp loop` off its cache) is
>> almost sure, and stop (or not) Ø1 because it's a don't care is a
>> possibility.
>
> Yes, R/W must be high, means reading from the external bus. But I don't
> know the state of the 6502 address bus in case of no bus cyle. If these
> even exist ...
>
>
> Regards, Ralf
> with poor quality of my copy of the Apple II schematics
I think Jorge is talking about an Apple II, and maybe a II+, but not a IIe.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354486 is a reply to message #354485] |
Sun, 15 October 2017 21:29 |
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Originally posted by: R.Kiefer.SPAEM
James Davis wrote:
> On Sunday, October 15, 2017 at 6:09:32 PM UTC-7, Ralf Kiefer wrote:
>> Jorge wrote:
>>
>>> In my Apple II *that* Ø1 is what gates the data bus transceivers on every
>>> write cycle, so... used it is used. Only that when R/W is high Ø1 is a
>>> don't care from the point of view of the bus transceivers.
>>
>> In the IIe and IIc PHASE1 (pin 3) and PHASE2 (pin 39) are not connected.
>> See Jim Sather, Understanding the Apple _IIe_, page 4.2.
^^^^^
>> But Jim Sather also wrote in Understanding the Apple _II_, page 4.2:
^^^^
>> "PHASE2 is not connected in the Apple. PHASE1 is used to control the
>> direction of the data flow in the external MPU data bus transceivers
>> during MPU write cycle."
> I think Jorge is talking about an Apple II, and maybe a II+, but not a IIe.
Yes, and there's the difference between these models.
Regards, Ralf
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354491 is a reply to message #354489] |
Sun, 15 October 2017 21:40 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 9:33:33 PM UTC-4, James Davis wrote:
> So, if phase-1 & phase-2 are not connected to anything on a IIe MLB, it does not mean that they cannot be tapped into (with small wires) for some other purpose/project, right? [(?) - picture an "idea" light-bulb.]
Right, though I presume you would need to wire them directly to the 6502 pins as Phase 1 and 2 do not exist on the peripheral bus.
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354493 is a reply to message #354491] |
Sun, 15 October 2017 21:45 |
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Originally posted by: James Davis
On Sunday, October 15, 2017 at 6:40:27 PM UTC-7, Anthony Ortiz wrote:
> On Sunday, October 15, 2017 at 9:33:33 PM UTC-4, James Davis wrote:
>> So, if phase-1 & phase-2 are not connected to anything on a IIe MLB, it does not mean that they cannot be tapped into (with small wires) for some other purpose/project, right? [(?) - picture an "idea" light-bulb.]
>
> Right, though I presume you would need to wire them directly to the 6502 pins as Phase 1 and 2 do not exist on the peripheral bus.
Yes, I said that, "phase-1 & phase-2 are not connected to anything on a IIe MLB . . . tapped into (with small wires) . . . ."
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354495 is a reply to message #354493] |
Sun, 15 October 2017 21:46 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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On Sunday, October 15, 2017 at 9:45:20 PM UTC-4, James Davis wrote:
> On Sunday, October 15, 2017 at 6:40:27 PM UTC-7, Anthony Ortiz wrote:
>> On Sunday, October 15, 2017 at 9:33:33 PM UTC-4, James Davis wrote:
>>> So, if phase-1 & phase-2 are not connected to anything on a IIe MLB, it does not mean that they cannot be tapped into (with small wires) for some other purpose/project, right? [(?) - picture an "idea" light-bulb.]
>>
>> Right, though I presume you would need to wire them directly to the 6502 pins as Phase 1 and 2 do not exist on the peripheral bus.
>
> Yes, I said that, "phase-1 & phase-2 are not connected to anything on a IIe MLB . . . tapped into (with small wires) . . . ."
You're right... I need some coffee!
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| Re: Apple II bus cycles when the ZipChip is running off cache [message #354506 is a reply to message #354451] |
Mon, 16 October 2017 05:07 |
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Originally posted by: Jorge
On Sunday, October 15, 2017 at 3:44:07 PM UTC+2, STYNX wrote:
>
> Any write to a memory location is synchronized with the Apple II memory. This is accomplished by the ZIP-ASIC and may even be buffered (but I doubt that). Sadly the ZIP-Chip ASIC has not been analyzed yet. Here are high resolution DIE shots: https://drive.google.com/open?id=0B5SAWSGa49rLamJSZTloVkphQj A
As anybody can see clearly just by looking at those pictures (lol) it drives A0-15 and R/W high.
I've just checked it right now with the 'scope. I run a `loop jmp loop` and it drives both R/W and A0-15 high, so it keeps reading $ffff in a loop.
Oh, and it does not stop driving Ø1, but does stop driving SYNC.
--
Jorge.
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