| CarteBlanche 16KB Ram card project [message #305436] |
Sat, 28 November 2015 16:06  |
a2retro
Messages: 76
Registered: June 2013
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I am studying the CBII 16KB ram card project as supplied on the AppleLogic web site. I have made a few changes to the source code and the ucf to make automatic assignment of pins easier.
I see in the UCF file there is only one user led. Are there any other that can be used by user programs?
Glenn
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| Re: CarteBlanche 16KB Ram card project [message #305439 is a reply to message #305437] |
Sat, 28 November 2015 19:02  |
a2retro
Messages: 76
Registered: June 2013
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On Saturday, November 28, 2015 at 6:00:07 PM UTC-5, Bill Garber wrote:
> "a2retro" <a2retrosystems@gmail.com> wrote in message
> news:fee2e417-8ee9-43d3-ada7-ac65e12b7185@googlegroups.com...
>> I am studying the CBII 16KB ram card project as supplied on the
>> AppleLogic web site. I have made a few changes to the source code
>> and the ucf to make automatic assignment of pins easier.
>
> Kool... That's what you're supposed to do... 8>)
>
>> I see in the UCF file there is only one user led. Are there any other
>> that can be used by user programs?
>
> An LED array came with them that plugs into the ZIF socket, or you
> could build your own on an expansion card and have all the LEDs that
> you would ever need.
>
> Bill Garber * http://www.sepa-electronics.com *
There are 4 leds on the board already, I was hoping i could access them all.
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| Re: CarteBlanche 16KB Ram card project [message #305441 is a reply to message #305439] |
Sat, 28 November 2015 19:51 |
Charlie
Messages: 255
Registered: November 2012
Karma: 0
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On 11/28/2015 7:02 PM, a2retro wrote:
> On Saturday, November 28, 2015 at 6:00:07 PM UTC-5, Bill Garber wrote:
>> "a2retro"<a2retrosystems@gmail.com> wrote in message
>> news:fee2e417-8ee9-43d3-ada7-ac65e12b7185@googlegroups.com...
>>> I am studying the CBII 16KB ram card project as supplied on the
>>> AppleLogic web site. I have made a few changes to the source code
>>> and the ucf to make automatic assignment of pins easier.
>>
>> Kool... That's what you're supposed to do... 8>)
>>
>>> I see in the UCF file there is only one user led. Are there any other
>>> that can be used by user programs?
>>
>> An LED array came with them that plugs into the ZIF socket, or you
>> could build your own on an expansion card and have all the LEDs that
>> you would ever need.
>>
>> Bill Garber * http://www.sepa-electronics.com *
>
> There are 4 leds on the board already, I was hoping i could access them all.
>
I believe the others are dedicated indicators for the CBII.
Charlie
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| Re: CarteBlanche 16KB Ram card project [message #371529 is a reply to message #305441] |
Thu, 02 August 2018 08:25 |
a2retro
Messages: 76
Registered: June 2013
Karma: 0
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I am looking at this project again (ISE 14.7) but having trouble getting a successful compile
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
SYSCLK
This may be due to either an insufficient number of sites available on the device, too many prohibited sites,
or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
This situation could possibly be resolved by one (or all) of the following actions:
a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
c) If applicable, decreasing the number of user prohibited sites or using a larger device.
SYSCLK is in the original code and not in the original constraints file. Does anyone know where this is generated from?
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| Re: CarteBlanche 16KB Ram card project [message #371537 is a reply to message #371529] |
Thu, 02 August 2018 11:22 |
Charlie
Messages: 255
Registered: November 2012
Karma: 0
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Senior Member |
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On 8/2/2018 8:25 AM, a2retro wrote:
> I am looking at this project again (ISE 14.7) but having trouble getting a successful compile
>
> ERROR:Place:866 - Not enough valid sites to place the following IOBs:
> IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
> SYSCLK
>
> This may be due to either an insufficient number of sites available on the device, too many prohibited sites,
> or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
> This situation could possibly be resolved by one (or all) of the following actions:
> a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
> b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
> c) If applicable, decreasing the number of user prohibited sites or using a larger device.
>
> SYSCLK is in the original code and not in the original constraints file. Does anyone know where this is generated from?
>
If you are using a Carte Blanche 1 then it is on pin 183 and the
constraints file (ucf file) should have something like this:
NET "SYSCLK" IOSTANDARD = LVCMOS33;
NET "SYSCLK" LOC = P183;
If you are using a Carte Blanche 2 then it is on pin D11 and the
constraints file (ucf file) should have something like this:
NET "SYSCLK" LOC=D11 | IOSTANDARD = "LVTTL";
NET "SYSCLK" CLOCK_DEDICATED_ROUTE = TRUE;
In the VHDL constraints file the name is CLK12M.
Record=Constraint | TargetKind=Port | TargetId=CLK12M | FPGA_PINNUM=D11
You can change CLK12M to SYSCLK if you want or change all instances of
SYSCLK to CLK12M in your code.
Hopefully that will fix your problem.
SYSCLK refers to the on-board oscillator which is 12 MHz on the CB-2 and
14.3 MHz on the CB-1.
Charlie
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| Re: CarteBlanche 16KB Ram card project [message #371660 is a reply to message #371537] |
Sat, 04 August 2018 15:21 |
a2retro
Messages: 76
Registered: June 2013
Karma: 0
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On Thursday, August 2, 2018 at 11:22:17 AM UTC-4, Charlie wrote:
> On 8/2/2018 8:25 AM, a2retro wrote:
>> I am looking at this project again (ISE 14.7) but having trouble getting a successful compile
>>
>> ERROR:Place:866 - Not enough valid sites to place the following IOBs:
>> IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
>> SYSCLK
>>
>> This may be due to either an insufficient number of sites available on the device, too many prohibited sites,
>> or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
>> This situation could possibly be resolved by one (or all) of the following actions:
>> a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
>> b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
>> c) If applicable, decreasing the number of user prohibited sites or using a larger device.
>>
>> SYSCLK is in the original code and not in the original constraints file. Does anyone know where this is generated from?
>>
>
> If you are using a Carte Blanche 1 then it is on pin 183 and the
> constraints file (ucf file) should have something like this:
>
> NET "SYSCLK" IOSTANDARD = LVCMOS33;
> NET "SYSCLK" LOC = P183;
>
> If you are using a Carte Blanche 2 then it is on pin D11 and the
> constraints file (ucf file) should have something like this:
>
> NET "SYSCLK" LOC=D11 | IOSTANDARD = "LVTTL";
> NET "SYSCLK" CLOCK_DEDICATED_ROUTE = TRUE;
>
> In the VHDL constraints file the name is CLK12M.
>
> Record=Constraint | TargetKind=Port | TargetId=CLK12M | FPGA_PINNUM=D11
>
> You can change CLK12M to SYSCLK if you want or change all instances of
> SYSCLK to CLK12M in your code.
>
> Hopefully that will fix your problem.
>
> SYSCLK refers to the on-board oscillator which is 12 MHz on the CB-2 and
> 14.3 MHz on the CB-1.
>
> Charlie
Hi Charlie, thank you for the reply. I was getting confused why the supplied ucf file had no SYSCLOCK reference.
This helps clear things up.
Btw - to emulate a peripheral card ROM do you suggest to add the data as an in memory array as part of the bit file or is there any other way?
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| Re: CarteBlanche 16KB Ram card project [message #371699 is a reply to message #371660] |
Sat, 04 August 2018 22:22 |
Charlie
Messages: 255
Registered: November 2012
Karma: 0
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Senior Member |
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On 8/4/2018 3:21 PM, a2retro wrote:
> On Thursday, August 2, 2018 at 11:22:17 AM UTC-4, Charlie wrote:
>> On 8/2/2018 8:25 AM, a2retro wrote:
>>> I am looking at this project again (ISE 14.7) but having trouble getting a successful compile
>>>
>>> ERROR:Place:866 - Not enough valid sites to place the following IOBs:
>>> IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
>>> SYSCLK
>>>
>>> This may be due to either an insufficient number of sites available on the device, too many prohibited sites,
>>> or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
>>> This situation could possibly be resolved by one (or all) of the following actions:
>>> a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
>>> b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
>>> c) If applicable, decreasing the number of user prohibited sites or using a larger device.
>>>
>>> SYSCLK is in the original code and not in the original constraints file. Does anyone know where this is generated from?
>>>
>>
>> If you are using a Carte Blanche 1 then it is on pin 183 and the
>> constraints file (ucf file) should have something like this:
>>
>> NET "SYSCLK" IOSTANDARD = LVCMOS33;
>> NET "SYSCLK" LOC = P183;
>>
>> If you are using a Carte Blanche 2 then it is on pin D11 and the
>> constraints file (ucf file) should have something like this:
>>
>> NET "SYSCLK" LOC=D11 | IOSTANDARD = "LVTTL";
>> NET "SYSCLK" CLOCK_DEDICATED_ROUTE = TRUE;
>>
>> In the VHDL constraints file the name is CLK12M.
>>
>> Record=Constraint | TargetKind=Port | TargetId=CLK12M | FPGA_PINNUM=D11
>>
>> You can change CLK12M to SYSCLK if you want or change all instances of
>> SYSCLK to CLK12M in your code.
>>
>> Hopefully that will fix your problem.
>>
>> SYSCLK refers to the on-board oscillator which is 12 MHz on the CB-2 and
>> 14.3 MHz on the CB-1.
>>
>> Charlie
>
> Hi Charlie, thank you for the reply. I was getting confused why the supplied ucf file had no SYSCLOCK reference.
>
> This helps clear things up.
>
> Btw - to emulate a peripheral card ROM do you suggest to add the data as an in memory array as part of the bit > file
That's how I would do it.
> or is there any other way?
You could initialize the 'ROM' from the CB flash memory (above the bit
file) but that is more complex than necessary and may not be finished
fast enough after powering up the Apple II.
Charlie
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