Message-ID: <7298@brl-tgr.ARPA>
Date: Mon, 14-Jan-85 07:31:31 EST
Article-I.D.: brl-tgr.7298
Posted: Mon Jan 14 07:31:31 1985
Date-Received: Wed, 16-Jan-85 16:17:04 EST
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Z800.DOC relayed from the RCPM circuit...
--cut here--

Zilog Z800 microprocessor chip quick description.

Hello folks out there in techie land, 

I just got in a new Zilog catalog and found the technical specs 
for  the Z800 chip.  I thought some out there might be interested
in a quick review of what seems to be a very nice chip.  Here  we
go...

The  Z800 family will be offered in 4 packages,  their  abilities
are:

1. address 512K bytes of memory on an eight bit data bus,
2. address 512K bytes of memory on a sixteen bit data bus,
3. address 16M  bytes of memory on an eight bit data bus,
4. address 16M  bytes of memory on a sixteen bit data bus.

Packages one and two are 40 pin, and 3 and 4 are 64 pin.

The chip is Z80 object code compatible

There is a 256 byte on chip memory that is configurable to cache 
or normal RAM.

The Z800 also has 4 DMA channels, 4 counter/timers, a dynamic RAM 
refresh generator,  a clock osc., a memory management unit, and a  
UART directly on the chip. (only the 64 pin version can access all 
features).

The  chip will support what Zilog calls Nibble mode addressing of 
chips, for faster accessing of RAM (I think Intel calls it Ripple 
mode, I could be wrong).

The bus interface could be handy for those of us who want to  use 
the  Z800 at the targeted 10MHz of the first chips Zilog will put
out, (25 Mhz later) even if we can only afford chips that can run 
at  four  or  five  MHz.  There is a timing control register that 
tells  the  CPU  that  Bus operations will be clocked at the same 
speed  as  the  CPU,  or  1/2 of the speed,  or 1/4 of the speed. 
There are also high and low  memory  wait state insertion bits if  
memory of mixed speeds is to be used.

There is an on chip single step mode.

There are 9 addressing modes:
1. Register,
2. Immediate,
3. Register Indirect,
4. Direct Address,
5. Index,
6. Short Index,               
7. Relative,                  
8. Stack Pointer Relative,    *
9. Base Index                 *
  * indicates new to Z800 (from Z80)

Looks to me like a super chip... can't wait 'till someone comes out with 
an add on board for my Kaypro 10 (hint's to those out there who are 
capable...)

Delivery according to the latest Echelon ZCPR3 Newsletter will start in 
April 1985. Wait and salivate...


                                                  Dave Olsen
                                                    1-8-85