| ][GS and DMA ram card. [message #382243] |
Wed, 20 March 2019 17:36  |
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Originally posted by: Leon Sargent
I am waiting for my MicroDrive / Turbo.
In the spec DMA noted and its performance benefits.
To have the full available benefits of DMA, the ram card must also support DMA?
Leon
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| Re: ][GS and DMA ram card. [message #382255 is a reply to message #382243] |
Wed, 20 March 2019 19:05  |
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Originally posted by: Anthony Adverse
On Thursday, March 21, 2019 at 8:36:10 AM UTC+11, Leon Sargent wrote:
> I am waiting for my MicroDrive / Turbo.
>
> In the spec DMA noted and its performance benefits.
>
> To have the full available benefits of DMA, the ram card must also support DMA?
>
> Leon
Interesting thought, that would make sense. I don't recall seeing any ram card 4MB or less, that is not DMA. The memory over 4Mb is not DMA compatible due to the GS ROM.
A
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| Re: ][GS and DMA ram card. [message #382319 is a reply to message #382255] |
Fri, 22 March 2019 10:54 |
Jeff Blakeney
Messages: 127
Registered: September 2013
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On 2019-03-20 7:05 p.m., Anthony Adverse wrote:
> Interesting thought, that would make sense. I don't recall seeing
> any ram card 4MB or less, that is not DMA. The memory over 4Mb is
> not DMA compatible due to the GS ROM.
I believe the limitation is due to the memory slot only having enough
special select lines to support up to 4 MB of DMA. Don't have my
manuals handy to look it up right now.
Now, not being able to use more than 8 MB of RAM, that is a limitation
of the ROM and apparently is a one byte fix that emulators can apply to
allow using up to 14 MB.
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| Re: ][GS and DMA ram card. [message #382403 is a reply to message #382319] |
Sun, 24 March 2019 17:50 |
Polymorph
Messages: 206
Registered: October 2012
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On Saturday, March 23, 2019 at 1:54:47 AM UTC+11, Jeff Blakeney wrote:
>
> Now, not being able to use more than 8 MB of RAM, that is a limitation
> of the ROM and apparently is a one byte fix that emulators can apply to
> allow using up to 14 MB.
I'm guessing this "one byte fix" doesn't work on real hardware, otherwise someone would have done it. I assume the IIgs is missing the required address lines for anything greater than 8mb?? I wonder how much effort would be required to hack the missing lines in (if even possible)?
Cheers,
Mike
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| Re: ][GS and DMA ram card. [message #382407 is a reply to message #382403] |
Sun, 24 March 2019 23:15 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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On Sunday, March 24, 2019 at 3:50:20 PM UTC-6, Polymorph wrote:
> On Saturday, March 23, 2019 at 1:54:47 AM UTC+11, Jeff Blakeney wrote:
>>
>> Now, not being able to use more than 8 MB of RAM, that is a limitation
>> of the ROM and apparently is a one byte fix that emulators can apply to
>> allow using up to 14 MB.
>
> I'm guessing this "one byte fix" doesn't work on real hardware, otherwise someone would have done it. I assume the IIgs is missing the required address lines for anything greater than 8mb?? I wonder how much effort would be required to hack the missing lines in (if even possible)?
>
> Cheers,
> Mike
I thought it was done? What became of someone making that 16 Mb Ramworks clone?
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| Re: ][GS and DMA ram card. [message #382412 is a reply to message #382407] |
Mon, 25 March 2019 03:16 |
Polymorph
Messages: 206
Registered: October 2012
Karma: 0
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On Monday, March 25, 2019 at 2:15:17 PM UTC+11, I am Rob wrote:
> On Sunday, March 24, 2019 at 3:50:20 PM UTC-6, Polymorph wrote:
>> On Saturday, March 23, 2019 at 1:54:47 AM UTC+11, Jeff Blakeney wrote:
>>>
>>> Now, not being able to use more than 8 MB of RAM, that is a limitation
>>> of the ROM and apparently is a one byte fix that emulators can apply to
>>> allow using up to 14 MB.
>>
>> I'm guessing this "one byte fix" doesn't work on real hardware, otherwise someone would have done it. I assume the IIgs is missing the required address lines for anything greater than 8mb?? I wonder how much effort would be required to hack the missing lines in (if even possible)?
>>
>> Cheers,
>> Mike
>
>
> I thought it was done? What became of someone making that 16 Mb Ramworks clone?
The RamWorks style cards are //e Aux memory cards, not compatible with the IIgs. What I was wondering is if it would be possible to hack a IIgs motherboard to support the ROM "one byte fix" to allow IIgs memory expansion cards greater than 8mb.
Cheers,
Mike
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| Re: ][GS and DMA ram card. [message #382428 is a reply to message #382403] |
Mon, 25 March 2019 11:21 |
Jeff Blakeney
Messages: 127
Registered: September 2013
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On 2019-03-24 5:50 p.m., Polymorph wrote:
> On Saturday, March 23, 2019 at 1:54:47 AM UTC+11, Jeff Blakeney
> wrote:
>>
>> Now, not being able to use more than 8 MB of RAM, that is a
>> limitation of the ROM and apparently is a one byte fix that
>> emulators can apply to allow using up to 14 MB.
>
> I'm guessing this "one byte fix" doesn't work on real
> hardware,otherwise someone would have done it. I assume the IIgs is
> missing the required address lines for anything greater than 8mb?? I
> wonder how much effort would be required to hack the missing lines in
> (if even possible)?
The one byte fix would work on real hardware but you would need to
replace your ROM chip. All the address lines are there but you will
still only get DMA to the first 4 MB of RAM unless the memory card is
designed to generate the missing select lines and I don't think any
memory card has done that.
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| Re: ][GS and DMA ram card. [message #382434 is a reply to message #382412] |
Mon, 25 March 2019 12:14 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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On Monday, March 25, 2019 at 1:16:05 AM UTC-6, Polymorph wrote:
> On Monday, March 25, 2019 at 2:15:17 PM UTC+11, I am Rob wrote:
>> On Sunday, March 24, 2019 at 3:50:20 PM UTC-6, Polymorph wrote:
>>> On Saturday, March 23, 2019 at 1:54:47 AM UTC+11, Jeff Blakeney wrote:
>>>>
>>>> Now, not being able to use more than 8 MB of RAM, that is a limitation
>>>> of the ROM and apparently is a one byte fix that emulators can apply to
>>>> allow using up to 14 MB.
>>>
>>> I'm guessing this "one byte fix" doesn't work on real hardware, otherwise someone would have done it. I assume the IIgs is missing the required address lines for anything greater than 8mb?? I wonder how much effort would be required to hack the missing lines in (if even possible)?
>>>
>>> Cheers,
>>> Mike
>>
>>
>> I thought it was done? What became of someone making that 16 Mb Ramworks clone?
>
> The RamWorks style cards are //e Aux memory cards, not compatible with the IIgs. What I was wondering is if it would be possible to hack a IIgs motherboard to support the ROM "one byte fix" to allow IIgs memory expansion cards greater than 8mb.
>
> Cheers,
> Mike
It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
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| Re: ][GS and DMA ram card. [message #382452 is a reply to message #382432] |
Mon, 25 March 2019 19:47 |
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Originally posted by: mike.stephens.kg
On Tuesday, March 26, 2019 at 3:04:33 AM UTC+11, wayne_j...@yahoo.ca wrote:
> A2heaven sells a ROM that he says supports 14mb. Of course you still need the RAM card.
Cool! I didn't know that this was possible. I wonder if Plamen will come up with a 14mb RAM card for the IIgs? I wouldn't put it past him. ;-)
Cheers,
Mike
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| Re: ][GS and DMA ram card. [message #382465 is a reply to message #382452] |
Tue, 26 March 2019 01:17 |
Antoine Vignau
Messages: 1860
Registered: October 2012
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Hi,
4MB DMA support is a h/w limitation.
Hi there,
8MB RAM support is a h/w limitation.
The 1-byte fix does not allow more RAM to be used, it just calculates the nb of RAM banks available to the system, but that does not make them real and usable.
Using 14MB is possible if you take control of what is on the bus and simulates a RAM card.
Antoine
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| Re: ][GS and DMA ram card. [message #382466 is a reply to message #382434] |
Tue, 26 March 2019 02:24 |
mdj
Messages: 301
Registered: December 2012
Karma: 0
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On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
> It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
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| Re: ][GS and DMA ram card. [message #382474 is a reply to message #382466] |
Tue, 26 March 2019 12:26 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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On Tuesday, March 26, 2019 at 12:24:38 AM UTC-6, mdj wrote:
> On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
>
>> It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
>
> The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
>
> As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
You lost me a little bit on this one as your explanation insinuates 4 Mb of contiguous memory. If that is so, then how does the Bank register come into play with 4 Mb of memory? And can DMA access all 4 Mb without the use of the bank register through the slots?
Sorry for my ignorance. My knowledge of the IIGS is pretty limited, so I need to compare to something I already understand, which is what was explained with the Auxiliary slot.
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| Re: ][GS and DMA ram card. [message #382479 is a reply to message #382474] |
Tue, 26 March 2019 19:13 |
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Originally posted by: Anthony Adverse
On Wednesday, March 27, 2019 at 3:26:08 AM UTC+11, I am Rob wrote:
> On Tuesday, March 26, 2019 at 12:24:38 AM UTC-6, mdj wrote:
>> On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
>>
>>> It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
>>
>> The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
>>
>> As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
>
>
> You lost me a little bit on this one as your explanation insinuates 4 Mb of contiguous memory. If that is so, then how does the Bank register come into play with 4 Mb of memory? And can DMA access all 4 Mb without the use of the bank register through the slots?
>
> Sorry for my ignorance. My knowledge of the IIGS is pretty limited, so I need to compare to something I already understand, which is what was explained with the Auxiliary slot.
The GS ram slot is a special case... a bit like the AUX slot but upgraded :) You can put 4 contiguous megs of ram in there, that's what it was designed for, after that you need some jiggery pokery to get the extra 4 meg in there which is why the top 4 don't do DMA...
<waiting to be shot down becuase its wrong>
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| Re: ][GS and DMA ram card. [message #382483 is a reply to message #382479] |
Tue, 26 March 2019 21:49 |
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Originally posted by: James Davis
On Tuesday, March 26, 2019 at 4:14:00 PM UTC-7, Anthony Adverse wrote:
> On Wednesday, March 27, 2019 at 3:26:08 AM UTC+11, I am Rob wrote:
>> On Tuesday, March 26, 2019 at 12:24:38 AM UTC-6, mdj wrote:
>>> On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
>>>
>>>> It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
>>>
>>> The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
>>>
>>> As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
>>
>>
>> You lost me a little bit on this one as your explanation insinuates 4 Mb of contiguous memory. If that is so, then how does the Bank register come into play with 4 Mb of memory? And can DMA access all 4 Mb without the use of the bank register through the slots?
>>
>> Sorry for my ignorance. My knowledge of the IIGS is pretty limited, so I need to compare to something I already understand, which is what was explained with the Auxiliary slot.
>
> The GS ram slot is a special case... a bit like the AUX slot but upgraded :) You can put 4 contiguous megs of ram in there, that's what it was designed for, after that you need some jiggery pokery to get the extra 4 meg in there which is why the top 4 don't do DMA...
>
> <waiting to be shot down becuase its wrong>
Sounds like the RAM card would have to bank switch two banks through software (Peek/Poke or Read/Write): e.g., Switch between 1M or 4M (Bank 1) with 1M or 4M (Bank 2), respectively, independent of the Apple IIGS software (firmware/ROM?).
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| Re: ][GS and DMA ram card. [message #382487 is a reply to message #382479] |
Tue, 26 March 2019 23:50 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Tuesday, March 26, 2019 at 5:14:00 PM UTC-6, Anthony Adverse wrote:
> On Wednesday, March 27, 2019 at 3:26:08 AM UTC+11, I am Rob wrote:
>> On Tuesday, March 26, 2019 at 12:24:38 AM UTC-6, mdj wrote:
>>> On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
>>>
>>>> It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
>>>
>>> The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
>>>
>>> As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
>>
>>
>> You lost me a little bit on this one as your explanation insinuates 4 Mb of contiguous memory. If that is so, then how does the Bank register come into play with 4 Mb of memory? And can DMA access all 4 Mb without the use of the bank register through the slots?
>>
>> Sorry for my ignorance. My knowledge of the IIGS is pretty limited, so I need to compare to something I already understand, which is what was explained with the Auxiliary slot.
>
> The GS ram slot is a special case... a bit like the AUX slot but upgraded :) You can put 4 contiguous megs of ram in there, that's what it was designed for, after that you need some jiggery pokery to get the extra 4 meg in there which is why the top 4 don't do DMA...
>
> <waiting to be shot down becuase its wrong>
You must be a politician cause you totally avoided the subject, which is DMA access to the extra GS RAM. :)
This is what I know from my 8 Mb Sirius card. You cannot access any of it without accessing the Bank Register, which is part of the IIGS ROM and not independent to the RAM card. The bank register could only go up to 128, which is 8 Mb's. The card also had extra space for chips that allowed a ROM disk to be stored on the card. The bank register had to access $D0.DF to access the ROM disk.
If a ROM disk can be expanded on the card with special chips, then the theoretical max of a RAM card should be $CF (208 banks of 64 kb)(13.3 Mb) + 16 banks of 64 kb for the ROM disk. The ROM disk could not be written to, and had to have eproms already made, but could be read from.
Now back to the original question. Can DMA access of a hard drive directly access all available RAM without accessing the bank register? If not, then the bank register is pretty much the same as the softswitch $C073, but has a little more direct access to the memory card.
Therefore, a hard drive can not directly store data to expanded RAM without either accessing the Bank register on a IIGS, or the $C073 softswitch on a IIe. This requires software in the firmware of hard drive card to be able to access all banks of the RAM card. And DMA is no more than a cleverly written firmware.
And lastly. The Ram chips themselves (whether 256 kb, 1 Mb or 4 Mb) may be contiguous memory, but accessing the RAM card is not. Or, does the data lines of the GS memory give direct access, bypassing the DATA register?
I might be overthinking this but until I get an answer that satisfies my curiosity, my curiosity bug keeps me awake at night.
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| Re: ][GS and DMA ram card. [message #382488 is a reply to message #382465] |
Wed, 27 March 2019 00:40 |
Jeff Blakeney
Messages: 127
Registered: September 2013
Karma: 0
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Senior Member |
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On 2019-03-26 1:17 a.m., Antoine Vignau wrote:
> Hi,
> 4MB DMA support is a h/w limitation.
>
> Hi there,
>
> 8MB RAM support is a h/w limitation.
>
> The 1-byte fix does not allow more RAM to be used, it just calculates the nb of RAM banks available to the system, but that does not make them real and usable.
>
> Using 14MB is possible if you take control of what is on the bus and simulates a RAM card.
Hmm, I was always under the impression that the memory expansion slot
had the 16 address lines and 8 data lines from the processor on it. The
65816 multiplexes the bank register on the data lines to give 24 address
bits total which gives access to 16 MB of memory space.
I just pulled out my IIgs Hardware Reference and it seems they did weird
things with the pins on the slot. It seems the FRA0-9 pins are used to
give 20 multiplexed address lines if using 1 Mb RAM chips. The A10-A15
pins look like they might be straight from the processor. 20 address
lines only give you access to 1 MB of memory so the CROW0 and CROW1 pins
let you select one of four "banks" of 1 MB giving access to 4 MB of RAM.
Why not just use A10 and A11 instead of CROW0 and CROW1. Its the same
thing, selecting which four of the 1 MB areas below it that you want to
access.
I never realized how dumb the memory slot was. You've got the 24 pins
being used anyway, why not just make them A0-A15 and D0-D7 and allow the
memory card to decode the address itself. I suppose conflicts with RAM
and ROM on the motherboard might be a problem but there had to be a
better way to handle it than they did.
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| Re: ][GS and DMA ram card. [message #382489 is a reply to message #382488] |
Wed, 27 March 2019 00:54 |
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Originally posted by: Leon Sargent
What a hot topic tonight!
Here is something I found which gives some interesting perspective..
From A2Heaven.
You can also use the Apple GSx ROM Adapter for experiment and firmware development.
We can also program other IIgs firmware on to the FLASH if requested .
Attention : you can't use this Adapter to upgrade a ROM0 or ROM1 IIgs system to ROM3 !
You can switch betwen four ROM-s pre programmed on Adapter. Notice line 2.
0 : ROM 00
1 : ROM 01
2: ROM 01 modified to support 14MB RAM module
3 : Custom ROM ( on request )
Leon
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| Re: ][GS and DMA ram card. [message #382494 is a reply to message #382487] |
Wed, 27 March 2019 11:11 |
Charlie
Messages: 256
Registered: November 2012
Karma: 0
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Senior Member |
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On 3/26/2019 11:50 PM, I am Rob wrote:
> On Tuesday, March 26, 2019 at 5:14:00 PM UTC-6, Anthony Adverse wrote:
>> On Wednesday, March 27, 2019 at 3:26:08 AM UTC+11, I am Rob wrote:
>>> On Tuesday, March 26, 2019 at 12:24:38 AM UTC-6, mdj wrote:
>>>> On Tuesday, 26 March 2019 02:14:31 UTC+10, I am Rob wrote:
>>>>
>>>> > It wasn't the card I was directly referring to, to work on a IIGS. I was indirectly referring to the Aux slot, if it has the address lines to support a 16 Mb memory card, then so should the IIGS memory slot.
>>>>
>>>> The Auxiliary slot only supports 64k - more memory on cards is achieved by bank switching the 64k space.
>>>>
>>>> As for the IIGS, the memory slot directly supports 4MB (strictly 4 banks of either 1MB or 256KB). With some trickery you can decode the next 4mb, but it's a hack, albeit a relatively simple one.
>>>
>>>
>>> You lost me a little bit on this one as your explanation insinuates 4 Mb of contiguous memory. If that is so, then how does the Bank register come into play with 4 Mb of memory? And can DMA access all 4 Mb without the use of the bank register through the slots?
>>>
>>> Sorry for my ignorance. My knowledge of the IIGS is pretty limited, so I need to compare to something I already understand, which is what was explained with the Auxiliary slot.
>>
>> The GS ram slot is a special case... a bit like the AUX slot but upgraded :) You can put 4 contiguous megs of ram in there, that's what it was designed for, after that you need some jiggery pokery to get the extra 4 meg in there which is why the top 4 don't do DMA...
>>
>> <waiting to be shot down becuase its wrong>
>
>
> You must be a politician cause you totally avoided the subject, which is DMA access to the extra GS RAM. :)
>
> This is what I know from my 8 Mb Sirius card. You cannot access any of it without accessing the Bank Register, >which is part of the IIGS ROM and not independent to the RAM card.
I don't understand what you mean. A register can't be part of ROM which
is Read Only Memory. It can't be changed so wouldn't be much use as a
register.
> The bank register could only go up to 128, which is 8 Mb's.
The IIgs does have a DMA bank register at $C037 and it can hold any
number from $0 to $FF, enough for 16 MB. However a RAM card doesn't
have any way to know what is in that register during DMA.
> The card also had extra space for chips that allowed a ROM disk to be stored on the card. The bank register had > to access $D0.DF to access the ROM disk.
>
> If a ROM disk can be expanded on the card with special chips, then the theoretical max of a RAM card should be $CF (208 banks of 64 kb)(13.3 Mb) + 16 banks of 64 kb for the ROM disk. The ROM disk could not be written to, and had to have eproms already made, but could be read from.
>
> Now back to the original question. Can DMA access of a hard drive directly access all available RAM without accessing the bank register? If not, then the bank register is pretty much the same as the softswitch $C073, but has a little more direct access to the memory card.
>
> Therefore, a hard drive can not directly store data to expanded RAM without either accessing the Bank register on a IIGS, or the $C073 softswitch on a IIe. This requires software in the firmware of hard drive card to be able to access all banks of the RAM card. And DMA is no more than a cleverly written firmware.
>
> And lastly. The Ram chips themselves (whether 256 kb, 1 Mb or 4 Mb) may be contiguous memory, but accessing the RAM card is not. Or, does the data lines of the GS memory give direct access, bypassing the DATA register?
>
> I might be overthinking this but until I get an answer that satisfies my curiosity, my curiosity bug keeps me awake at night.
>
If I understand IIgs Technote #21 correctly, it is possible for a RAM
expansion card to latch the bank address from the data bus. This method
seems to allow up to 16 MB of RAM but it does not help with DMA because
only the last CPU cycle's bank address will be left on the data bus.
Charlie
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| Re: ][GS and DMA ram card. [message #382500 is a reply to message #382494] |
Wed, 27 March 2019 14:43 |
Antoine Vignau
Messages: 1860
Registered: October 2012
Karma: 0
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Senior Member |
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From hw ref volume 2:
page 51: ram above 4 MB cannot be accessed via fma
page 176: dma done through banks 0 to 4f (79)
page 198: dma, at full speed, through banks 0 to 7f (127)
pfew... John!!!!
av
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| Re: ][GS and DMA ram card. [message #382509 is a reply to message #382494] |
Wed, 27 March 2019 17:39 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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>> This is what I know from my 8 Mb Sirius card. You cannot access any of it without accessing the Bank Register, >which is part of the IIGS ROM and not independent to the RAM card.
>
> I don't understand what you mean. A register can't be part of ROM which
> is Read Only Memory. It can't be changed so wouldn't be much use as a
> register.
I realized that after I hit send. I was trying to think of the individual parts of the motherboard. The data register would be part of the CPU.
>> The bank register could only go up to 128, which is 8 Mb's.
>
> The IIgs does have a DMA bank register at $C037 and it can hold any
> number from $0 to $FF, enough for 16 MB. However a RAM card doesn't
> have any way to know what is in that register during DMA.
So you are saying that DMA bypasses the bank register?
Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>> The card also had extra space for chips that allowed a ROM disk to be stored on the card. The bank register had > to access $D0.DF to access the ROM disk.
>>
>> If a ROM disk can be expanded on the card with special chips, then the theoretical max of a RAM card should be $CF (208 banks of 64 kb)(13.3 Mb) + 16 banks of 64 kb for the ROM disk. The ROM disk could not be written to, and had to have eproms already made, but could be read from.
>>
>> Now back to the original question. Can DMA access of a hard drive directly access all available RAM without accessing the bank register? If not, then the bank register is pretty much the same as the softswitch $C073, but has a little more direct access to the memory card.
>>
>> Therefore, a hard drive can not directly store data to expanded RAM without either accessing the Bank register on a IIGS, or the $C073 softswitch on a IIe. This requires software in the firmware of hard drive card to be able to access all banks of the RAM card. And DMA is no more than a cleverly written firmware.
>>
>> And lastly. The Ram chips themselves (whether 256 kb, 1 Mb or 4 Mb) may be contiguous memory, but accessing the RAM card is not. Or, does the data lines of the GS memory give direct access, bypassing the DATA register?
>>
>> I might be overthinking this but until I get an answer that satisfies my curiosity, my curiosity bug keeps me awake at night.
>>
>
> If I understand IIgs Technote #21 correctly, it is possible for a RAM
> expansion card to latch the bank address from the data bus. This method
> seems to allow up to 16 MB of RAM but it does not help with DMA because
> only the last CPU cycle's bank address will be left on the data bus.
I think we have established that DMA bypasses the data register of the cpu, correct?
So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
Back to the original question. What is stopping DMA from accessing RAM above 4 Mb? The RAM card should not have any problems receiving data up to the 16 Mb limit through DMA or otherwise. The hard drive should not have any problems sending data up to the 16 Mb limit through DMA or otherwise.
Therefore, it has to be the slots that are restricting data flow. But as stated, there are enough data lines to support 16 Mb of data.
Where do we go from here?
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| Re: ][GS and DMA ram card. [message #382510 is a reply to message #382500] |
Wed, 27 March 2019 17:41 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Wednesday, March 27, 2019 at 12:43:05 PM UTC-6, Antoine Vignau wrote:
> From hw ref volume 2:
> page 51: ram above 4 MB cannot be accessed via fma
> page 176: dma done through banks 0 to 4f (79)
> page 198: dma, at full speed, through banks 0 to 7f (127)
>
> pfew... John!!!!
> av
That definitely seems to be a conflict of interest as dma cannot go above 4 Mb which is 64 banks.
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| Re: ][GS and DMA ram card. [message #382514 is a reply to message #382500] |
Wed, 27 March 2019 19:28 |
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Originally posted by: jbrooks
On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
> From hw ref volume 2:
> page 51: ram above 4 MB cannot be accessed via fma
> page 176: dma done through banks 0 to 4f (79)
> page 198: dma, at full speed, through banks 0 to 7f (127)
>
> pfew... John!!!!
> av
The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
In order for a 14MB memory expansion to work correctly it would need to:
1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
> So you are saying that DMA bypasses the bank register?
The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
> I think we have established that DMA bypasses the data register of the cpu, correct?
Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped.
> What is stopping DMA from accessing RAM above 4 Mb?
The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
Hope that helps,
-JB
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| Re: ][GS and DMA ram card. [message #382518 is a reply to message #382509] |
Wed, 27 March 2019 21:34 |
Charlie
Messages: 256
Registered: November 2012
Karma: 0
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Senior Member |
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On 3/27/2019 5:39 PM, I am Rob wrote:
>
>>> This is what I know from my 8 Mb Sirius card. You cannot access any of it without accessing the Bank Register, >which is part of the IIGS ROM and not independent to the RAM card.
>>
>> I don't understand what you mean. A register can't be part of ROM which
>> is Read Only Memory. It can't be changed so wouldn't be much use as a
>> register.
>
>
> I realized that after I hit send. I was trying to think of the individual parts of the motherboard. The data register would be part of the CPU.
>
>
>>> The bank register could only go up to 128, which is 8 Mb's.
>>
>> The IIgs does have a DMA bank register at $C037 and it can hold any
>> number from $0 to $FF, enough for 16 MB. However a RAM card doesn't
>> have any way to know what is in that register during DMA.
>
>
> So you are saying that DMA bypasses the bank register?
The bank register (bus) yes because the it is a function of the CPU
which is stopped during DMA. The DMA bank register is (I assume) set
by the firmware of the DMA device that is doing the reading/writing.
I have no idea how it does that with the CPU stopped.
I'm no expert on hardware so I'll defer to John on that.
His explanation in another part of this thread clears up a lot.
> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
I imagine it was cheaper to make it that way.
>>> The card also had extra space for chips that allowed a ROM disk to be stored on the card. The bank register had > to access $D0.DF to access the ROM disk.
>>>
>>> If a ROM disk can be expanded on the card with special chips, then the theoretical max of a RAM card should be $CF (208 banks of 64 kb)(13.3 Mb) + 16 banks of 64 kb for the ROM disk. The ROM disk could not be written to, and had to have eproms already made, but could be read from.
>>>
>>> Now back to the original question. Can DMA access of a hard drive directly access all available RAM without accessing the bank register? If not, then the bank register is pretty much the same as the softswitch $C073, but has a little more direct access to the memory card.
>>>
>>> Therefore, a hard drive can not directly store data to expanded RAM without either accessing the Bank register on a IIGS, or the $C073 softswitch on a IIe. This requires software in the firmware of hard drive card to be able to access all banks of the RAM card. And DMA is no more than a cleverly written firmware.
>>>
>>> And lastly. The Ram chips themselves (whether 256 kb, 1 Mb or 4 Mb) may be contiguous memory, but accessing the RAM card is not. Or, does the data lines of the GS memory give direct access, bypassing the DATA register?
>>>
>>> I might be overthinking this but until I get an answer that satisfies my curiosity, my curiosity bug keeps me awake at night.
>>>
>>
>> If I understand IIgs Technote #21 correctly, it is possible for a RAM
>> expansion card to latch the bank address from the data bus. This method
>> seems to allow up to 16 MB of RAM but it does not help with DMA because
>> only the last CPU cycle's bank address will be left on the data bus.
>
>
> I think we have established that DMA bypasses the data register of the cpu, correct?
Yes.
> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
Yes.
> Back to the original question. What is stopping DMA from accessing RAM above 4 Mb? The RAM card should not have any problems receiving data up to the 16 Mb limit through DMA or otherwise. The hard drive should not have any problems sending data up to the 16 Mb limit through DMA or otherwise.
I think John has covered that much better than I could ever do.
> Therefore, it has to be the slots that are restricting data flow. But as stated, there are enough data lines to support 16 Mb of data.
>
> Where do we go from here?
>
John has given some ideas of how to do it.
However, for what its worth, I've been using my IIgs ROM 01 since about
1986 or 1987 and in all that time I've never run out of memory on my
4MB RAM expansion card.
Charlie
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| Re: ][GS and DMA ram card. [message #382519 is a reply to message #382514] |
Wed, 27 March 2019 21:35 |
Charlie
Messages: 256
Registered: November 2012
Karma: 0
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Senior Member |
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On 3/27/2019 7:28 PM, jbrooks@blueshiftinc.com wrote:
> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>> From hw ref volume 2:
>> page 51: ram above 4 MB cannot be accessed via fma
>> page 176: dma done through banks 0 to 4f (79)
>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>
>> pfew... John!!!!
>> av
>
> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>
> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>
> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>
> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>
> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>
> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>
> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>
> In order for a 14MB memory expansion to work correctly it would need to:
>
> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>
> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>
>
>> So you are saying that DMA bypasses the bank register?
>
> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>
> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>
>
>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>
> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>
>
>> I think we have established that DMA bypasses the data register of the cpu, correct?
>
> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>
>
>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>
> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped.
>
>
>> What is stopping DMA from accessing RAM above 4 Mb?
>
> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>
>
> Hope that helps,
> -JB
>
It does help. Very good explanation.
Charlie
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| Re: ][GS and DMA ram card. [message #382520 is a reply to message #382514] |
Wed, 27 March 2019 22:00 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Wednesday, March 27, 2019 at 5:28:47 PM UTC-6, jbr...@blueshiftinc.com wrote:
> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>> From hw ref volume 2:
>> page 51: ram above 4 MB cannot be accessed via fma
>> page 176: dma done through banks 0 to 4f (79)
>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>
>> pfew... John!!!!
>> av
>
> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>
> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>
> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>
> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>
> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>
> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>
> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>
> In order for a 14MB memory expansion to work correctly it would need to:
>
> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>
> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>
>
>> So you are saying that DMA bypasses the bank register?
>
> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>
> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>
>
>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>
> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>
>
>> I think we have established that DMA bypasses the data register of the cpu, correct?
>
> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>
>
>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>
> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped..
>
>
>> What is stopping DMA from accessing RAM above 4 Mb?
>
> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>
>
> Hope that helps,
> -JB
Yay! I can sleep tonight.
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| Re: ][GS and DMA ram card. [message #382521 is a reply to message #382514] |
Wed, 27 March 2019 22:07 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Wednesday, March 27, 2019 at 5:28:47 PM UTC-6, jbr...@blueshiftinc.com wrote:
> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>> From hw ref volume 2:
>> page 51: ram above 4 MB cannot be accessed via fma
>> page 176: dma done through banks 0 to 4f (79)
>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>
>> pfew... John!!!!
>> av
>
> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>
> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>
> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>
> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>
> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>
> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>
> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>
> In order for a 14MB memory expansion to work correctly it would need to:
>
> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>
> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>
>
>> So you are saying that DMA bypasses the bank register?
>
> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>
> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>
>
>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>
> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>
>
>> I think we have established that DMA bypasses the data register of the cpu, correct?
>
> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>
>
>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>
> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped..
>
>
>> What is stopping DMA from accessing RAM above 4 Mb?
>
> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>
>
> Hope that helps,
> -JB
Just one more question if I may?
Do DMA transfers support 16-bit (2 byte) data moves or just 1-byte?
The reason I ask this is because I find I am getting slightly faster reads/writes with Rich Drehers CFFA card than with the DMA transfer rates that have been posted from time to time.
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| Re: ][GS and DMA ram card. [message #382522 is a reply to message #382521] |
Wed, 27 March 2019 22:11 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Wednesday, March 27, 2019 at 8:07:55 PM UTC-6, I am Rob wrote:
> On Wednesday, March 27, 2019 at 5:28:47 PM UTC-6, jbr...@blueshiftinc.com wrote:
>> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>>> From hw ref volume 2:
>>> page 51: ram above 4 MB cannot be accessed via fma
>>> page 176: dma done through banks 0 to 4f (79)
>>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>>
>>> pfew... John!!!!
>>> av
>>
>> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>>
>> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>>
>> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>>
>> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>>
>> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>>
>> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>>
>> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>>
>> In order for a 14MB memory expansion to work correctly it would need to:
>>
>> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>>
>> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>>
>>
>>> So you are saying that DMA bypasses the bank register?
>>
>> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>>
>> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>>
>>
>>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>>
>> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>>
>>
>>> I think we have established that DMA bypasses the data register of the cpu, correct?
>>
>> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>>
>>
>>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>>
>> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped.
>>
>>
>>> What is stopping DMA from accessing RAM above 4 Mb?
>>
>> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>>
>>
>> Hope that helps,
>> -JB
>
>
> Just one more question if I may?
>
> Do DMA transfers support 16-bit (2 byte) data moves or just 1-byte?
>
> The reason I ask this is because I find I am getting slightly faster reads/writes with Rich Drehers CFFA card than with the DMA transfer rates that have been posted from time to time.
Oh! and one more question. Faster processor cards don't increase the speed of DMA, do they? Or will a faster CPU increase the North Bridge speed as well?
Sorry! I'm on a roll here.
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| Re: ][GS and DMA ram card. [message #382523 is a reply to message #382521] |
Thu, 28 March 2019 00:45 |
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Originally posted by: jbrooks
On Wednesday, March 27, 2019 at 7:07:55 PM UTC-7, I am Rob wrote:
> On Wednesday, March 27, 2019 at 5:28:47 PM UTC-6, jbr...@blueshiftinc.com wrote:
>> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>>> From hw ref volume 2:
>>> page 51: ram above 4 MB cannot be accessed via fma
>>> page 176: dma done through banks 0 to 4f (79)
>>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>>
>>> pfew... John!!!!
>>> av
>>
>> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>>
>> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>>
>> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>>
>> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>>
>> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>>
>> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>>
>> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>>
>> In order for a 14MB memory expansion to work correctly it would need to:
>>
>> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>>
>> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>>
>>
>>> So you are saying that DMA bypasses the bank register?
>>
>> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>>
>> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>>
>>
>>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>>
>> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>>
>>
>>> I think we have established that DMA bypasses the data register of the cpu, correct?
>>
>> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>>
>>
>>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>>
>> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped.
>>
>>
>>> What is stopping DMA from accessing RAM above 4 Mb?
>>
>> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>>
>>
>> Hope that helps,
>> -JB
>
>
> Just one more question if I may?
>
> Do DMA transfers support 16-bit (2 byte) data moves or just 1-byte?
>
> The reason I ask this is because I find I am getting slightly faster reads/writes with Rich Drehers CFFA card than with the DMA transfer rates that have been posted from time to time.
DMA (and all IIGS DRAM chips) are 8-bit, so there are no 2-byte data moves per cycle. The VGC's video display is a special case in that it accesses 4x separate 8-bit DRAMS per cycle to achieve 32-bit bandwidth (displaying 160 SHR bytes in 40 usec every scanline).
Apple does mention the possibility of slot cards being able to DMA at 2.8MHz, but since the slot cards have only a 1MHz PH0 and a 7MHz clock, they would need to generate their own 2.8MHz PH2 clock from 7MHz, and also account for the FPI/CYA DRAM refresh stalls, so it would be very tricky to get right.
The 65816 is a static CMOS device and can have its clock stopped indefinitely during DMA without losing register state (PC, stack, etc). However, the NMOS 6502 in the II, II+, and original IIe can only have its clock stopped for 10 usec before losing register state.
Since most DMA slot cards were designed to work in the original IIe with an NMOS 6502, they DMA for a burst of 1 to 10 cycles, and then have a normal non-DMA cycle to refresh the CPU state. The result is that simple DMA implementations run at 1/2 of max throughput (1 DMA then 1 normal cycle). DMA bursts of 8 cycles are also common. Max bandwidth for NMOS 6502 is 10 DMA every 11 cycles = 91% utilization of the 1MHz bus.
Fast CPU accelerators like the A2Heaven FastChip, ZipGS, or TWGS run so fast they can achieve 100% utilization of the 1MHz slot card bus when accessing slot I/O such as the CFFA, and as a result can provide better throughput than the many slot card DMA implementations.
When I implemented the DMA memory move in VidHD's firmware ($Cs11 AuxMove), there are two speeds the DMA can operate at: 91% efficient 10-DMA bursts for NMOS 6502 machines, or 100% efficient unlimited-length bursts for CMOS 65c02 & 65c816 machines .
> Faster processor cards don't increase the speed of DMA, do they?
No
> Or will a faster CPU increase the North Bridge speed as well?
No, but the accelerator cards can access high-speed cache memory for all the 65816 opcode fetches and only access the slow 1 MHz DRAM for writes, softswitch & I/O, and cache-miss reads.
-JB
@JBrooksBSI
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| Re: ][GS and DMA ram card. [message #382524 is a reply to message #382488] |
Thu, 28 March 2019 08:13 |
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Originally posted by: Delfs
The IIgs ram is accessed by the the CPU by sending out the top 8 address bits on the data line just prior to accessing memory. The CYA/FPI chip controls the address lines on the main board and keeps this (bank) data to itself. With 24 lines one can access up to 16M of linear memory.
Anyway, at the memory slot, the CYA/FPI chip adjusts the ‘bank’ byte by however much RAM is built into the machine so the original one is offset by 4, the ROM3 offset by 16. The chip only puts out 2 select lines instead of 8 bank address lines.
The IIgs was deliberately crippled by Apple so it would not compete with the Mac line of the time. The 6800 was removed as an option, the upper half of the memory was dedicated to Rom like the Mac as it had Mac engineers. The ram slot and clock speed was deliberately limited.
There should have been a byte in memory dedicated to the Upper 8 bits of the address, the memory expansion slot should have had all the bank lines present.
It could have buried a Mac of the day 128 times over.
He’s an idea I’ve been toying with for years. FPI snap in/ CYA snap-on that is a a full speed 20MHz CPU with 16M SRAM or Flash. (Pull CPU out)
Additional circuits;
Address bank register/latch (available)
Choose‘Rom’ location for this byte to show if read.
Load Rom from main board on cold start
Synch to main board clock (available) monitors speed memory location.
Clock only runs while FPI/CYA is low clock in CPU.
Notes: never accessed onboard lowest 128k, always goes to main board. Always drops to main board speed when using 0,1, E0 and E1 memory banks.
-Ed
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| Re: ][GS and DMA ram card. [message #382529 is a reply to message #382523] |
Thu, 28 March 2019 12:29 |
gids.rs
Messages: 1395
Registered: October 2012
Karma: 0
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Senior Member |
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On Wednesday, March 27, 2019 at 10:45:23 PM UTC-6, jbr...@blueshiftinc.com wrote:
> On Wednesday, March 27, 2019 at 7:07:55 PM UTC-7, I am Rob wrote:
>> On Wednesday, March 27, 2019 at 5:28:47 PM UTC-6, jbr...@blueshiftinc.com wrote:
>>> On Wednesday, March 27, 2019 at 11:43:05 AM UTC-7, Antoine Vignau wrote:
>>>> From hw ref volume 2:
>>>> page 51: ram above 4 MB cannot be accessed via fma
>>>> page 176: dma done through banks 0 to 4f (79)
>>>> page 198: dma, at full speed, through banks 0 to 7f (127)
>>>>
>>>> pfew... John!!!!
>>>> av
>>>
>>> The North Bridge (NB) chips, FPA (ROM0/1) and CYA (ROM3), control the 65816 PH2 clock speed (1M vs 2.8M) and most of the signals on the Memory Expansion Slot (MES). A memory access through the MES is controlled by the /CSEL line and is only activated by the NB when banks $02-$7F and banks $F0-$FD (on ROM0/1) are accessed by the CPU or DMA.
>>>
>>> A card in the MES can contain ROM and/or DRAM with the type of memory being accessed controlled by /CROMSEL. DRAM accesses have 2 lines (CROW0, CROW1) to control which of 4 DRAM banks are being accessed.
>>>
>>> However, the NB will also access the MES for accesses between 4MB and 8MB, but since there are only 2 bank lines, accesses to the upper 4MB will mirror to the lower 4MB.
>>>
>>> The 8MB memory cards rely on this mirroring and do their own decoding of the bank address, which is multiplexed onto the data bus, to decide whether the 65816 is accessing the upper 4MB or the lower 4MB. They effectively synthesize a CROW2 line to allow CPU access to dual 4MB memory regions.
>>>
>>> During DMA, the NB controls the MES DRAM banks directly via CROW0/1, allowing only 4MB of DMA-compatible memory access.
>>>
>>> Unfortunately, during DMA the NB has to stop the PH2 clock of the 65816 (and MES), and since the slot cards have only a 1MHz 16-bit bus, there is not a valid bank address being multiplexed onto the data bus for the memory card to decode (and no PH2 clock either). This leaves an 8MB card blind as to which of the 4MB regions is being accessed since it only gets CROW0/1 from the NB chip.
>>>
>>> As long as DMA is only performed to the lower 4MB, then an 8MB card can rely on the NB signals to allow CPU access to the upper 4MB and CPU+DMA access to the lower 4MB.
>>>
>>> In order for a 14MB memory expansion to work correctly it would need to:
>>>
>>> 1) Plug into one of the 7 slots so it could watch the DMA line and PH0 1Mhz clock
>>>
>>> 2) Plug into the CPU socket so it could watch the full 24-bit CPU address without the NB interfering and also to allow access to banks $80-$DF. This means the CPU would need to be on the memory card, similar to some IIc expansion cards.
>>>
>>>
>>>> So you are saying that DMA bypasses the bank register?
>>>
>>> The DMA bank register is located inside the NB chip and is used during DMA to decide whether a DMA transfer should go to the Mega2, MB ROM, MB DRAM, MES ROM, or MES DRAM, and which DRAM bank is being accessed.
>>>
>>> During DMA, the CPU's PH2 clock is stopped, so the memory card has to rely on /CSEL to know when its ROM or DRAM is being accessed. DRAM accesses have only CROW0/1 and so are limited to 4MB.
>>>
>>>
>>>> Anything beyond bank $80 (#128) is ignored for the RAM card. The question why is still unanswered?
>>>
>>> Almost certainly for the NB's ease-of-decoding. A23=1 means MB/MES ROM or Mega2, and A23=0 means DRAM or in banks 0/1 it could mean shadowed MB ROM/DRAM/Mega2.
>>>
>>>
>>>> I think we have established that DMA bypasses the data register of the cpu, correct?
>>>
>>> Yes, during DMA the 65816 PH2 clock is stopped and the CPU is not active on either the address or data bus.
>>>
>>>
>>>> So we are talking the transfer of data from the hard drive directly to the memory card with no motherboard CPU intervention, correct?
>>>
>>> The NB controls DMA to MB or MES DRAM directly with the CPU clock stopped.
>>>
>>>
>>>> What is stopping DMA from accessing RAM above 4 Mb?
>>>
>>> The NB & MES would need 2 more bank lines, CROW2 & CROW3 to allow 16x 1MB banks. Or the MES would need to have a valid 24-bit address on every access and it would have to decode to RAS/CAS itself.
>>>
>>>
>>> Hope that helps,
>>> -JB
>>
>>
>> Just one more question if I may?
>>
>> Do DMA transfers support 16-bit (2 byte) data moves or just 1-byte?
>>
>> The reason I ask this is because I find I am getting slightly faster reads/writes with Rich Drehers CFFA card than with the DMA transfer rates that have been posted from time to time.
>
> DMA (and all IIGS DRAM chips) are 8-bit, so there are no 2-byte data moves per cycle. The VGC's video display is a special case in that it accesses 4x separate 8-bit DRAMS per cycle to achieve 32-bit bandwidth (displaying 160 SHR bytes in 40 usec every scanline).
>
> Apple does mention the possibility of slot cards being able to DMA at 2.8MHz, but since the slot cards have only a 1MHz PH0 and a 7MHz clock, they would need to generate their own 2.8MHz PH2 clock from 7MHz, and also account for the FPI/CYA DRAM refresh stalls, so it would be very tricky to get right.
>
> The 65816 is a static CMOS device and can have its clock stopped indefinitely during DMA without losing register state (PC, stack, etc). However, the NMOS 6502 in the II, II+, and original IIe can only have its clock stopped for 10 usec before losing register state.
>
> Since most DMA slot cards were designed to work in the original IIe with an NMOS 6502, they DMA for a burst of 1 to 10 cycles, and then have a normal non-DMA cycle to refresh the CPU state. The result is that simple DMA implementations run at 1/2 of max throughput (1 DMA then 1 normal cycle). DMA bursts of 8 cycles are also common. Max bandwidth for NMOS 6502 is 10 DMA every 11 cycles = 91% utilization of the 1MHz bus.
>
> Fast CPU accelerators like the A2Heaven FastChip, ZipGS, or TWGS run so fast they can achieve 100% utilization of the 1MHz slot card bus when accessing slot I/O such as the CFFA, and as a result can provide better throughput than the many slot card DMA implementations.
>
> When I implemented the DMA memory move in VidHD's firmware ($Cs11 AuxMove), there are two speeds the DMA can operate at: 91% efficient 10-DMA bursts for NMOS 6502 machines, or 100% efficient unlimited-length bursts for CMOS 65c02 & 65c816 machines .
>
>
>> Faster processor cards don't increase the speed of DMA, do they?
>
> No
>
>
>> Or will a faster CPU increase the North Bridge speed as well?
>
> No, but the accelerator cards can access high-speed cache memory for all the 65816 opcode fetches and only access the slow 1 MHz DRAM for writes, softswitch & I/O, and cache-miss reads.
>
> -JB
> @JBrooksBSI
Thanks! That's enough. I feel like I can almost build my own computer now, or write my own book.
But I am definitely bookmarking this thread for future reference.
You know! "BROOKS" isn't a bad name for an Apple clone computer. Just saying.
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| Re: ][GS and DMA ram card. [message #382548 is a reply to message #382523] |
Thu, 28 March 2019 22:53 |
Christopher G. Mason
Messages: 156
Registered: November 2012
Karma: 0
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Senior Member |
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On 3/28/2019 12:45 AM, jbrooks@blueshiftinc.com wrote:
> Fast CPU accelerators like the A2Heaven FastChip, ZipGS, or TWGS run so fast they can achieve 100% utilization of the 1MHz slot card bus when accessing slot I/O such as the CFFA, and as a result can provide better throughput than the many slot card DMA implementations.
IF this is the case, how the heck is the RamFAST Rev D so damned fast
(even with 30 year old mechanical hard drives) compared to the DMA-less
CFFA3000 (using much faster solid state storage) in my TWGS equipped
IIgs? Aggressive caching only gets one so far, the cards still have to
transfer the data to RAM.
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| Re: ][GS and DMA ram card. [message #382563 is a reply to message #382488] |
Fri, 29 March 2019 17:17 |
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Originally posted by: kegs
In article <q7eus2$3qe$1@dont-email.me>,
Jeff Blakeney <CUTjeffrey_blakeney@yahoo.ca> wrote:
> On 2019-03-26 1:17 a.m., Antoine Vignau wrote:
>> Hi,
>> 4MB DMA support is a h/w limitation.
>>
>> Hi there,
>>
>> 8MB RAM support is a h/w limitation.
>>
>> The 1-byte fix does not allow more RAM to be used, it just calculates
> the nb of RAM banks available to the system, but that does not make them
> real and usable.
>>
>> Using 14MB is possible if you take control of what is on the bus and
> simulates a RAM card.
>
>
> Hmm, I was always under the impression that the memory expansion slot
> had the 16 address lines and 8 data lines from the processor on it. The
> 65816 multiplexes the bank register on the data lines to give 24 address
> bits total which gives access to 16 MB of memory space.
>
> I just pulled out my IIgs Hardware Reference and it seems they did weird
> things with the pins on the slot. It seems the FRA0-9 pins are used to
> give 20 multiplexed address lines if using 1 Mb RAM chips. The A10-A15
> pins look like they might be straight from the processor. 20 address
> lines only give you access to 1 MB of memory so the CROW0 and CROW1 pins
> let you select one of four "banks" of 1 MB giving access to 4 MB of RAM.
> Why not just use A10 and A11 instead of CROW0 and CROW1. Its the same
> thing, selecting which four of the 1 MB areas below it that you want to
> access.
>
> I never realized how dumb the memory slot was. You've got the 24 pins
> being used anyway, why not just make them A0-A15 and D0-D7 and allow the
> memory card to decode the address itself. I suppose conflicts with RAM
> and ROM on the motherboard might be a problem but there had to be a
> better way to handle it than they did.
The memory slot is clever in that it allows a dumb memory card to work in
a ROM01 or ROM03 IIgs.
In a ROM01, there is motherboard memory for banks $01,$02 only (we'll ignore
$e0,$e1 memory for this since it doesn't really involve the RAM slot).
In a ROM03, there is motherboard memory for banks $01-$0f.
So what the IIgs does is give a decoded address to the RAM slot that already
takes into account the motherboard memory. The first byte of RAM slot
memory is $02_0000 on a ROM01, but it's $10_0000 on a ROM03. The RAM slot
doesn't tell the card what the ROM type is. By already decoding the
address (effectively, subtracting out $02 or $10 from the bank address), the
the RAM cards stay really simple since the decoding was done for it already--
it just connects up the address signals to the DRAM chips and it's done.
This works for four banks of 1MB each or four banks of 256KB each.
Note, this means a ROM01 can DMA to memory from bank $00 through bank $42.
And a ROM03 can DMA to memory from bank $00 through bank $4f. This is because
the bank decode is done properly for these addresses.
It's possible to do more decode on the RAM slot, to support 8MB of memory,
since it can see the bank address fully. This is more complex, but clearly
doable (these cards exist). This may not have been practical when the IIgs
first released, though, due to the speed of the decoding.
The 8MB limitation is a ROM limit--the ROM just doesn't check for memory
above bank $7f, so it doesn't make it available through any Tool call.
With the "1-byte" ROM fix, a special RAM card decoding the full bank address
can support memory to 14MB. There may be other hardware limitations, I
just don't know.
Kent
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