| False read on index mode write? [message #372840] |
Sun, 26 August 2018 02:26  |
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Originally posted by: John Pham
Just wondering what are some of the quirks of 6502
does this STA (someaddress),Y cause a false read
on someaddress - is the 6502 put the someaddress on the bus
and do a someaddress + y so it doesn't have to do internal addition ?
but if I do LDA (someaddress),y - there is no double read on someaddress?
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| False read on index mode write? [message #372845 is a reply to message #372840] |
Sun, 26 August 2018 10:16  |
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Originally posted by: Thomas Harte
An indirect indexed STA will always take six cycles; the first four to fetch the instruction, the zero-page address, then the two-byte base from the zero page. It will then add Y to the low byte of the address and read from there — it'll read because that may or may not be the correct address and it considers a read to be harmless. It'll then correct the high byte if necessary, and do the store.
A LDA will be either five or six cycles — if the high byte was already correct it won't bother spending a cycle on reading again.
So you'll always get the false read on a store, but it may be from the wrong address — it may be a page too low, if there needs to be carry into the high byte. You'll get a false read on a load only if there needs to be carry.
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| Re: False read on index mode write? [message #372851 is a reply to message #372845] |
Sun, 26 August 2018 12:53 |
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Originally posted by: John Pham
On Sunday, August 26, 2018 at 7:16:56 AM UTC-7, Thomas Harte wrote:
> An indirect indexed STA will always take six cycles; the first four to fetch the instruction, the zero-page address, then the two-byte base from the zero page. It will then add Y to the low byte of the address and read from there — it'll read because that may or may not be the correct address and it considers a read to be harmless. It'll then correct the high byte if necessary, and do the store.
>
it's not harmless, it's a damn bug - imagine you do a sta device,Y only to read the data on device so you're missing a char every time you do a write to that device
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| Re: False read on index mode write? [message #372852 is a reply to message #372845] |
Sun, 26 August 2018 14:18 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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Thomas Harte <thomas.harte@gmail.com> wrote:
> An indirect indexed STA will always take six cycles; the first four to
> fetch the instruction, the zero-page address, then the two-byte base from
> the zero page. It will then add Y to the low byte of the address and read
> from there — it'll read because that may or may not be the correct
> address and it considers a read to be harmless. It'll then correct the
> high byte if necessary, and do the store.
>
> A LDA will be either five or six cycles — if the high byte was already
> correct it won't bother spending a cycle on reading again.
>
> So you'll always get the false read on a store, but it may be from the
> wrong address — it may be a page too low, if there needs to be carry into
> the high byte. You'll get a false read on a load only if there needs to be carry.
>
And the same logic applies to the absolute indexed mode, with timings of 4
and 5 cycles for non-stores and always 5 cycles for stores.
Indexed stores always do an extra read, but to the lower page if indexing
causes a page crossing.
This suggests a strategy for avoiding redundant reads from a memory mapped
I/O page: arrange for the access to cross a page boundary so the extra
read doesn’t hit the I/O page.
This is an occasionally annoying behavior which is a consequence of a
fundamental design decision in the 6502—that memory is accessed on every
cycle. This decision simplified its logic and seldom is an issue, since it
is well documented.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: False read on index mode write? [message #372857 is a reply to message #372851] |
Sun, 26 August 2018 15:29 |
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Originally posted by: Thomas Harte
On Sunday, 26 August 2018 12:53:11 UTC-4, John Pham wrote:
> On Sunday, August 26, 2018 at 7:16:56 AM UTC-7, Thomas Harte wrote:
>> An indirect indexed STA will always take six cycles; the first four to fetch the instruction, the zero-page address, then the two-byte base from the zero page. It will then add Y to the low byte of the address and read from there — it'll read because that may or may not be the correct address and it considers a read to be harmless. It'll then correct the high byte if necessary, and do the store.
>>
>
> it's not harmless, it's a damn bug - imagine you do a sta device,Y only to read the data on device so you're missing a char every time you do a write to that device
Right; maybe least harmful thing the 6502 designers could think of within their constraints would be more accurate?
Having double checked the 65C02's datasheet, correction of this behaviour — the 65C02 will reread the final instruction byte rather than reading from the wrong address — is described diplomatically only as an "operational enhancement", though it's the very first thing on the list. Above even elimination of the opcode that just send the original 6502 into an uninterruptible spin.
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