| Transwarp - How do they work? [message #347789] |
Sat, 08 July 2017 10:35  |
anthonypaulo
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I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
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| Re: Transwarp - How do they work? [message #347830 is a reply to message #347789] |
Sat, 08 July 2017 19:56  |
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Originally posted by: John Brooks
On Saturday, July 8, 2017 at 7:35:57 AM UTC-7, Anthony Ortiz wrote:
> I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
The Transwarp & Zip accelerators plug into the CPU socket, replacing the original CPU.
Since the accelerator board contains it's own faster CPU, and there is no longer a CPU on the motherboard, there is no problem 'taking over completely'.
-JB
@JBrooksBSI
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| Re: Transwarp - How do they work? [message #347831 is a reply to message #347830] |
Sat, 08 July 2017 20:31 |
gbody4
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For the slot based accelerators which don't use the CPU socket, it is most likely they are using the DMA signal to disable the on board 6502. This allows the 6502/65c02 on the card to control the system. This can limit the use of other DMA based cards in the system.
Regards
Geoff B
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| Re: Transwarp - How do they work? [message #347832 is a reply to message #347831] |
Sat, 08 July 2017 20:34 |
anthonypaulo
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On Saturday, July 8, 2017 at 8:31:18 PM UTC-4, geoff body wrote:
> For the slot based accelerators which don't use the CPU socket, it is most likely they are using the DMA signal to disable the on board 6502. This allows the 6502/65c02 on the card to control the system. This can limit the use of other DMA based cards in the system.
>
> Regards
> Geoff B
Yes, it seems DMA is how it's accomplishing the disabling of the on-board CPU. I happened to come across some info on it earlier today but you and Michael Mahon (who messaged me privately) are indeed correct.
Thanks!
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| Re: Transwarp - How do they work? [message #347876 is a reply to message #347789] |
Sun, 09 July 2017 13:07 |
STYNX
Messages: 453
Registered: October 2012
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On Saturday, July 8, 2017 at 4:35:57 PM UTC+2, Anthony Ortiz wrote:
> I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
There are 2 concepts being used in Apple II accelerators.
1. Caching
2. Shadowing
The ZIP CHIP and McT SpeedDemon use caching and all other accelerator use shadowing.
Caching is 'relatively' simple. It has a small full speed cache-memory that allows full speed access for data that has already been read at least once.. Every memory-write is done into the cache as well as the A2-memory (there may be some exceptions like the zero-page). Reading a byte can be done from the cache at full speed or from the memory at 1Mhz. Emptying the whole cache is not problematic as it will get filled again by normal usage. The main problem are the rules that map the memory locations to the cache. The zip-chip has 8kb of cache and must map up to 128k of memory locations. This needs highly optimized logic to allow a good acceleration.
Shadowing replaces some memory locations completely with full speed shadow-memory. Some memory locations must be written into the A2-memory (video, text...) and bank switching must be mapped as well. The whole process can get a bit complicated but allows relatively linear acceleration. A memory-shadow must have at least the same amount of memory as the host-system. (128k for the Apple //e)
-Jonas
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| Re: Transwarp - How do they work? [message #349629 is a reply to message #347876] |
Fri, 28 July 2017 12:01 |
anthonypaulo
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This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
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| Re: Transwarp - How do they work? [message #349630 is a reply to message #349629] |
Fri, 28 July 2017 12:33 |
Tom Greene
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Registered: January 2013
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On Friday, July 28, 2017 at 12:01:43 PM UTC-4, Anthony Ortiz wrote:
> This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.
Tom
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| Re: Transwarp - How do they work? [message #349637 is a reply to message #349630] |
Fri, 28 July 2017 13:46 |
anthonypaulo
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On Friday, July 28, 2017 at 12:33:56 PM UTC-4, Tom Greene wrote:
> On Friday, July 28, 2017 at 12:01:43 PM UTC-4, Anthony Ortiz wrote:
>> This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
>
> For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.
>
> Tom
Ahhhhh, good one.... that makes sense, for the disk drive at least. I wonder what scheme they used for the serial port and other timing-critical peripherals.
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| Re: Transwarp - How do they work? [message #349640 is a reply to message #349630] |
Fri, 28 July 2017 14:30 |
STYNX
Messages: 453
Registered: October 2012
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On Friday, July 28, 2017 at 6:33:56 PM UTC+2, Tom Greene wrote:
> On Friday, July 28, 2017 at 12:01:43 PM UTC-4, Anthony Ortiz wrote:
>> This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
>
> For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.
>
> Tom
There are several memory-locations to be monitored. Speaker and Paddle fro example, to name two. The method to slow down itself is dependent on the developer of the accelerator. You could simply 'stop' the cpu on the accelerator for a part of the 1Mhz cycle or add a delay of a bunch of nanoseconds (200-300ns). If you want to go all out, you can implement a buffer for some memory locations (audio, paddles for example) or even use a dual port memory with intelligent synchronization.
-Jonas
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| Re: Transwarp - How do they work? [message #349646 is a reply to message #349629] |
Fri, 28 July 2017 16:17 |
Michael J. Mahon
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Registered: October 2012
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> This brings up another question... how are they able to slow down to 1mhz
> speeds every time they access the peripherals (ie. memory mapped IO
> addresses) and maintain that speed during critical timing loops that it
> may know nothing about (such as disk access code) and speed up to full
> acceleration the rest of the time? I wonder what happened to those guys
> at AE, would love to see them in the groups and pick their brain.
>
It's not AE. Cache technology for the Apple II was developed first for the
SpeedDemon plug-in card, and later applied by the same folks in the Zip
Chip.
Apple eventually adopted the Zip Chip design (but not packaging) for the
IIc+.
TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
less elegant solution than caching, since smaller SRAMs can always be made
faster than large ones (which is why multi-level caches are now universal).
The card/multi-chip package detects accesses to certain I/O addresses, like
slot 6, and then runs synchronously with the 1MHz clock for a certain
length of time. Since the timing-critical code regularly accesses /DEVSEL
addresses, the processor remains slowed down until (in the case of slots)
about 50 milliseconds after the last access to a "slow" address.
This is documented in the Zip Chip documentation text file on the utility
disk.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #349654 is a reply to message #349646] |
Fri, 28 July 2017 18:50 |
anthonypaulo
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On Friday, July 28, 2017 at 4:17:15 PM UTC-4, Michael J. Mahon wrote:
> It's not AE. Cache technology for the Apple II was developed first for the
> SpeedDemon plug-in card, and later applied by the same folks in the Zip
> Chip.
> Apple eventually adopted the Zip Chip design (but not packaging) for the
> IIc+.
>
> TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
> less elegant solution than caching, since smaller SRAMs can always be made
> faster than large ones (which is why multi-level caches are now universal).
>
>
> The card/multi-chip package detects accesses to certain I/O addresses, like
> slot 6, and then runs synchronously with the 1MHz clock for a certain
> length of time. Since the timing-critical code regularly accesses /DEVSEL
> addresses, the processor remains slowed down until (in the case of slots)
> about 50 milliseconds after the last access to a "slow" address.
>
> This is documented in the Zip Chip documentation text file on the utility
> disk.
>
> --
> -michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Wow, thanks Michael! They don't call you the "Woz Humbler" for nothing! :P A friend of mine and I didn't know how they did it, so I thought about it a bit and figured that if I had to do this myself I would synchronize to the slow clock until x amount of time from the last access to a slow location, so I'm happy that we came about the same solution.
They must synchronize to the same 1mhz clock right? Otherwise I don't see how they would get an exact match since Apple does that elongated cycle thing every 65th cycle. I figure the various DOS's must factor that elongated cycle into their timings, but I don't know anything about that subject yet as my Beneath Apple DOS and ProDos books have yet to arrive.
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| Re: Transwarp - How do they work? [message #349656 is a reply to message #349654] |
Fri, 28 July 2017 19:34 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> On Friday, July 28, 2017 at 4:17:15 PM UTC-4, Michael J. Mahon wrote:
>> It's not AE. Cache technology for the Apple II was developed first for the
>> SpeedDemon plug-in card, and later applied by the same folks in the Zip
>> Chip.
>> Apple eventually adopted the Zip Chip design (but not packaging) for the
>> IIc+.
>>
>> TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
>> less elegant solution than caching, since smaller SRAMs can always be made
>> faster than large ones (which is why multi-level caches are now universal).
>>
>>
>> The card/multi-chip package detects accesses to certain I/O addresses, like
>> slot 6, and then runs synchronously with the 1MHz clock for a certain
>> length of time. Since the timing-critical code regularly accesses /DEVSEL
>> addresses, the processor remains slowed down until (in the case of slots)
>> about 50 milliseconds after the last access to a "slow" address.
>>
>> This is documented in the Zip Chip documentation text file on the utility
>> disk.
>>
>> --
>> -michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
>
> Wow, thanks Michael! They don't call you the "Woz Humbler" for nothing!
> :P A friend of mine and I didn't know how they did it, so I thought about
> it a bit and figured that if I had to do this myself I would synchronize
> to the slow clock until x amount of time from the last access to a slow
> location, so I'm happy that we came about the same solution.
>
> They must synchronize to the same 1mhz clock right? Otherwise I don't see
> how they would get an exact match since Apple does that elongated cycle
> thing every 65th cycle. I figure the various DOS's must factor that
> elongated cycle into their timings, but I don't know anything about that
> subject yet as my Beneath Apple DOS and ProDos books have yet to arrive.
>
It's even simpler.
Transitions in digital systems are driven by clock edges, so if it's time
to run synchronously with the 1MHz clock, you just switch to the slow
clock.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #349693 is a reply to message #349637] |
Sat, 29 July 2017 01:43 |
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Originally posted by: James Davis
On Friday, July 28, 2017 at 10:46:42 AM UTC-7, Anthony Ortiz wrote:
> Ahhhhh, good one.... that makes sense, for the disk drive at least. I wonder what scheme they used for the serial port and other timing-critical peripherals.
IIRC, with my Zip-Chip, I could configure it to slow down for any slots I needed it to do so for.
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| Re: Transwarp - How do they work? [message #351348 is a reply to message #351347] |
Thu, 24 August 2017 15:46 |
Michael J. Mahon
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Registered: October 2012
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> Wait a second... I would think that *any* access to the address bus would
> need to slow down to 1mhz, otherwise how would, say, a 16 MHz transwarp
> access data on a 1mhz bus at 16mhz?
>
Of course it slows down on any bus access. But accelerators work by
minimizing accesses to the slow bus.
For software controlling timing-sensitive devices, not just bus access, but
instruction execution needs to be slowed down to 1MHz, even though the
instructions are running from the accelerator's fast memory. This is why
the slots containing such devices need to be "marked" as slow.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351349 is a reply to message #351348] |
Thu, 24 August 2017 16:10 |
anthonypaulo
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Yes, that I understand, but what I've been hearing here is that only certain IO locations are monitored for a slow-down, such as the disk motor on/off switches, paddle, speaker, etc... however, I would think that *any* address bus access due to it not being cached/shadowed by the transwarp (that includes all of the IO address space right?) would need to slow down to 1mhz, so it's not just a select few locations that slow it down.
Or am I missing something?
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| Re: Transwarp - How do they work? [message #351378 is a reply to message #351349] |
Fri, 25 August 2017 01:46 |
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Originally posted by: awanderin
Anthony Ortiz <anthonypaulo@gmail.com> writes:
> Yes, that I understand, but what I've been hearing here is that only
> certain IO locations are monitored for a slow-down, such as the disk
> motor on/off switches, paddle, speaker, etc... however, I would think
> that *any* address bus access due to it not being cached/shadowed by
> the transwarp (that includes all of the IO address space right?) would
> need to slow down to 1mhz, so it's not just a select few locations
> that slow it down.
>
> Or am I missing something?
I think the missing piece is that when an accelerator detects a
reference to the "slow-down" I/O locations, it actually turns off
acceleration for a certain amount of time. The amount of time depends
upon the I/O location accessed. I think the ZipChip documentation would
make clear how long these delays are before the accelerator returns to
full speed.
--
Jerry awanderin at gmail dot com
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| Re: Transwarp - How do they work? [message #351380 is a reply to message #351349] |
Fri, 25 August 2017 03:24 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
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Anthony Ortiz <anthonypaulo@gmail.com> wrote:
> Yes, that I understand, but what I've been hearing here is that only
> certain IO locations are monitored for a slow-down, such as the disk
> motor on/off switches, paddle, speaker, etc... however, I would think
> that *any* address bus access due to it not being cached/shadowed by the
> transwarp (that includes all of the IO address space right?) would need
> to slow down to 1mhz, so it's not just a select few locations that slow it down.
>
> Or am I missing something?
>
Yes, *all* bus accesses are slow, all the time.
The issue is how the accelerator determines that it must *keep* running
*everything* slow for a while for speed-critical devices. This is done
heuristically by detecting references to certain I/O locations.
So they always slow down to access anything on the bus, but only when they
detect "magic" address references do they *keep* running slow (even from
fast memory) until a certain amount of time has passed or until some other
"magic" address is referenced.
Accelerators (or at least their bus interface logic) must always access the
bus at 1MHz, but they have to be told (somehow) whether to stop
accelerating for a while when running driver software for certain slot
devices. The only reason that accelerators accelerate is that they can
avoid accessing the Apple bus most of the time.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351381 is a reply to message #351378] |
Fri, 25 August 2017 03:24 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
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awanderin <awanderin@gmail.com> wrote:
> Anthony Ortiz <anthonypaulo@gmail.com> writes:
>
>> Yes, that I understand, but what I've been hearing here is that only
>> certain IO locations are monitored for a slow-down, such as the disk
>> motor on/off switches, paddle, speaker, etc... however, I would think
>> that *any* address bus access due to it not being cached/shadowed by
>> the transwarp (that includes all of the IO address space right?) would
>> need to slow down to 1mhz, so it's not just a select few locations
>> that slow it down.
>>
>> Or am I missing something?
>
> I think the missing piece is that when an accelerator detects a
> reference to the "slow-down" I/O locations, it actually turns off
> acceleration for a certain amount of time. The amount of time depends
> upon the I/O location accessed. I think the ZipChip documentation would
> make clear how long these delays are before the accelerator returns to
> full speed.
>
> --
> Jerry awanderin at gmail dot com
>
Exactly, and these times are determined heuristically based on the maximum
time that a driver can be active without another access to one of the
"magic" device addresses.
For example, during a 5.25" disk operation, the Zip Chip slows down to 1MHz
for about 50 milliseconds anytime an address in the /DEVSEL range ($C0sx)
is referenced, and, empirically, there will always be another reference
before the 50 milliseconds expires as long as data is being transferred.
For references to the speaker toggle ($C030), the slowdown is only a few
milliseconds (it's in the Zip Chip documentation), which means that audio
tones that toggle the speaker less than a few milliseconds apart will have
their correct "1MHz" pitch, but a slow "tick, tick" will be partially
accelerated.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351393 is a reply to message #351380] |
Fri, 25 August 2017 08:54 |
anthonypaulo
Messages: 531
Registered: September 2013
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Okay, thanks for clarifying, this is in accordance with my thought process as well; the accelerator must slow down for all bus accesses but will stay slow a bit for a select few locations. Does the Transwarp document these locations as well? If not I'll check out the Zip Chip docs.
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| Re: Transwarp - How do they work? [message #351394 is a reply to message #351378] |
Fri, 25 August 2017 09:12 |
Steven Hirsch
Messages: 798
Registered: October 2012
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On 08/25/2017 01:46 AM, awanderin wrote:
> Anthony Ortiz <anthonypaulo@gmail.com> writes:
>
>> Yes, that I understand, but what I've been hearing here is that only
>> certain IO locations are monitored for a slow-down, such as the disk
>> motor on/off switches, paddle, speaker, etc... however, I would think
>> that *any* address bus access due to it not being cached/shadowed by
>> the transwarp (that includes all of the IO address space right?) would
>> need to slow down to 1mhz, so it's not just a select few locations
>> that slow it down.
>>
>> Or am I missing something?
>
> I think the missing piece is that when an accelerator detects a
> reference to the "slow-down" I/O locations, it actually turns off
> acceleration for a certain amount of time. The amount of time depends
> upon the I/O location accessed. I think the ZipChip documentation would
> make clear how long these delays are before the accelerator returns to
> full speed.
Not sure about ZipChip, but on the original (IIe) TransWarp the length of the
slowdown is determined by RC time constant. I recall fiddling with this on
one of mine to minimize slow time.
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| Re: Transwarp - How do they work? [message #351413 is a reply to message #351394] |
Fri, 25 August 2017 14:30 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
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Steven Hirsch <snhirsch@gmail.com> wrote:
> On 08/25/2017 01:46 AM, awanderin wrote:
>> Anthony Ortiz <anthonypaulo@gmail.com> writes:
>>
>>> Yes, that I understand, but what I've been hearing here is that only
>>> certain IO locations are monitored for a slow-down, such as the disk
>>> motor on/off switches, paddle, speaker, etc... however, I would think
>>> that *any* address bus access due to it not being cached/shadowed by
>>> the transwarp (that includes all of the IO address space right?) would
>>> need to slow down to 1mhz, so it's not just a select few locations
>>> that slow it down.
>>>
>>> Or am I missing something?
>>
>> I think the missing piece is that when an accelerator detects a
>> reference to the "slow-down" I/O locations, it actually turns off
>> acceleration for a certain amount of time. The amount of time depends
>> upon the I/O location accessed. I think the ZipChip documentation would
>> make clear how long these delays are before the accelerator returns to
>> full speed.
>
> Not sure about ZipChip, but on the original (IIe) TransWarp the length of the
> slowdown is determined by RC time constant. I recall fiddling with this on
> one of mine to minimize slow time.
>
>
Interesting.
The lengths of the Zip Chip's "synchronous sequences" are set by a digital
timer on the ASIC--more reliable and much more compact. This is, of course,
the implementation of the IIc+ as well.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351414 is a reply to message #351394] |
Fri, 25 August 2017 15:33 |
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Originally posted by: R.Kiefer.SPAEM
Steven Hirsch wrote:
> Not sure about ZipChip, but on the original (IIe) TransWarp the length of the
> slowdown is determined by RC time constant. I recall fiddling with this on
> one of mine to minimize slow time.
Why do you want to do that? The Transwarp can slow down each slot if
necessary. You switch the accelerated mode on or off with the DIP
switches. So you won't loose too much performance if you shorten the
time for a single slot e.g. the disk controller. But you must be sure
that the driver code must not be accelerated too early.
My accelerator board is hard wired to slow down only for slot 6. No
jumpers, no DIP switches. So I cannot add a second disk controller
without changing driver code. This doesn't matter. Other slots are
filled with printer card, SSC, 80col, RamFactor, other RAM cards, 6522
card. There is no problem.
RWTS must be slow, the other drivers may be fast.
- Ralf
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| Re: Transwarp - How do they work? [message #351415 is a reply to message #351393] |
Fri, 25 August 2017 15:33 |
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Originally posted by: R.Kiefer.SPAEM
Anthony Ortiz wrote:
> Okay, thanks for clarifying, this is in accordance with my thought process
> as well; the accelerator must slow down for all bus accesses but will
> stay slow a bit for a select few locations.
Every accelerator must do that. The fast processor must synchronize to
the applebus and wait for the beginning of the 500nsec window to access
anything on the mainboard. Probably the fast processor has to wait
900nsec because a bit too late to fetch the previous window.
> Does the Transwarp document these locations as well?
That's not necessary. There are DIP switches. You can select every slot
to slow down the code as long as the build-in timer is running. Read the
manual! Applied Engineering described the functions of the DIP switches
well.
In detail: if the code which is running accelerated by the Transwarp's
processor wants to access any address from $C0En (the registers of the
disk controller in slot 6) and slot 6 is set to "slow" the code will run
at 1MHz as long as the internal Transwarp timer is counting. Every
following access to any address from $C0En will restart this timer.
If a slot is set to "fast" the code slows down just for the single
access of one cycle which reads from or writes to the slot. The slot
interface must wait until the beginning of a new 500nsec cycle to do the
slow bus cycle.
My accelerator board (a very rare one from West Germany) slows down just
for reading. Write access to the apple bus is buffered and is done in
background and parallel without interaction of the fast processor. Just
in case of too many accesses to the apple bus the fast processor must
wait until the bus interface has finished the old "order". This happens
from time to time because the fast processor runs at 12.5MHz.
- Ralf
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| Re: Transwarp - How do they work? [message #351425 is a reply to message #351415] |
Fri, 25 August 2017 16:46 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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Ralf Kiefer <R.Kiefer.SPAEM@gmx.de> wrote:
> Anthony Ortiz wrote:
>
>> Okay, thanks for clarifying, this is in accordance with my thought process
>> as well; the accelerator must slow down for all bus accesses but will
>> stay slow a bit for a select few locations.
>
> Every accelerator must do that. The fast processor must synchronize to
> the applebus and wait for the beginning of the 500nsec window to access
> anything on the mainboard. Probably the fast processor has to wait
> 900nsec because a bit too late to fetch the previous window.
>
>
>> Does the Transwarp document these locations as well?
>
> That's not necessary. There are DIP switches. You can select every slot
> to slow down the code as long as the build-in timer is running. Read the
> manual! Applied Engineering described the functions of the DIP switches
> well.
>
> In detail: if the code which is running accelerated by the Transwarp's
> processor wants to access any address from $C0En (the registers of the
> disk controller in slot 6) and slot 6 is set to "slow" the code will run
> at 1MHz as long as the internal Transwarp timer is counting. Every
> following access to any address from $C0En will restart this timer.
>
> If a slot is set to "fast" the code slows down just for the single
> access of one cycle which reads from or writes to the slot. The slot
> interface must wait until the beginning of a new 500nsec cycle to do the
> slow bus cycle.
>
> My accelerator board (a very rare one from West Germany) slows down just
> for reading. Write access to the apple bus is buffered and is done in
> background and parallel without interaction of the fast processor. Just
> in case of too many accesses to the apple bus the fast processor must
> wait until the bus interface has finished the old "order". This happens
> from time to time because the fast processor runs at 12.5MHz.
>
> - Ralf
>
The Zip Chip (and IIc+) also buffer writes. Of course, if the write buffer
is not empty by the time the next read occurs, it stalls until the write
buffer is empty (to preserve ordering).
One note, apparently the "slowdown" delay on the Transwarp is a
retriggerable monostable rather than a counter.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351427 is a reply to message #351425] |
Fri, 25 August 2017 18:30 |
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Originally posted by: R.Kiefer.SPAEM
Michael J. Mahon <mjmahon@aol.com> wrote:
> One note, apparently the "slowdown" delay on the Transwarp is a
> retriggerable monostable rather than a counter.
Ok, Steven Hirsch mentioned that before. If you write or analyze code
there's no difference. You cannot change the delay with code.
It seems to be the 74LS123 near the left edge connected to the resistor
at the left corner (150kOhm) and the capacity (10uF) nearby. Reading
this document (page 9)
http://www.ti.com/lit/an/sdla006a/sdla006a.pdf
means: the delay is valid for about 650msec? Hm, anything wrong with my
observation?
I've got a photo (from the Apple II Documentation Project) and I looked
onto my own TransWarp: the resistor and the capacity are the same.
650msec are very long. More than 3 rotations of the floppy disk ...
- Ralf
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| Re: Transwarp - How do they work? [message #351431 is a reply to message #351427] |
Fri, 25 August 2017 20:29 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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Ralf Kiefer <R.Kiefer.SPAEM@gmx.de> wrote:
> Michael J. Mahon <mjmahon@aol.com> wrote:
>
>> One note, apparently the "slowdown" delay on the Transwarp is a
>> retriggerable monostable rather than a counter.
>
> Ok, Steven Hirsch mentioned that before. If you write or analyze code
> there's no difference. You cannot change the delay with code.
>
> It seems to be the 74LS123 near the left edge connected to the resistor
> at the left corner (150kOhm) and the capacity (10uF) nearby. Reading
> this document (page 9)
> http://www.ti.com/lit/an/sdla006a/sdla006a.pdf
>
> means: the delay is valid for about 650msec? Hm, anything wrong with my
> observation?
>
> I've got a photo (from the Apple II Documentation Project) and I looked
> onto my own TransWarp: the resistor and the capacity are the same.
>
> 650msec are very long. More than 3 rotations of the floppy disk ...
Yes, that's *way* too long.
I suspect that the 10uF capacitor is a filter/bypass capacitor on the +5v,
not a timing capacitor.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351433 is a reply to message #351431] |
Fri, 25 August 2017 22:25 |
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Originally posted by: R.Kiefer.SPAEM
Michael J. Mahon wrote:
> I suspect that the 10uF capacitor is a filter/bypass capacitor on the +5v,
> not a timing capacitor.
Sorry, no. "-" of that capacitor is connected to GND, but "+" is
connected to Vcc via the resistor (150kOhm) and to pin 7 of the LS123.
You can recognize this connection on the component side.
Pin 6 of the LS123 is connected to GND. This is the "traditional" usage
of the LS123 as described in the TI documentation mentioned before.
There is just one question: is this the delay generation?
It's a bit more complicated :-( The first half of the LS123 is used
also in this context. Pin 4 and pin 5 of the LS123 are connected to the
LS32, pin 1 and pin 2. The next question: the function of that first
half LS123. Pin 15 is connected to the capacitor nearby marked with
"330" (nF ?). This capacitor is connected to Vcc via 110kOhm if switch 8
of block 1 is open (3.6MHz) or connected to Vcc via 10kOhm if switch 8
of block 1 is closed (1.7MHz).
That's too curious, so I'm probably wrong :-(
BTW the capacitor between the processor and the EPROM is also used for
timing purpose.
- Ralf
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| Re: Transwarp - How do they work? [message #351434 is a reply to message #351433] |
Fri, 25 August 2017 23:05 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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Ralf Kiefer <R.Kiefer.SPAEM@gmx.de> wrote:
> Michael J. Mahon wrote:
>
>> I suspect that the 10uF capacitor is a filter/bypass capacitor on the +5v,
>> not a timing capacitor.
>
> Sorry, no. "-" of that capacitor is connected to GND, but "+" is
> connected to Vcc via the resistor (150kOhm) and to pin 7 of the LS123.
> You can recognize this connection on the component side.
>
> Pin 6 of the LS123 is connected to GND. This is the "traditional" usage
> of the LS123 as described in the TI documentation mentioned before.
>
> There is just one question: is this the delay generation?
>
> It's a bit more complicated :-( The first half of the LS123 is used
> also in this context. Pin 4 and pin 5 of the LS123 are connected to the
> LS32, pin 1 and pin 2. The next question: the function of that first
> half LS123. Pin 15 is connected to the capacitor nearby marked with
> "330" (nF ?). This capacitor is connected to Vcc via 110kOhm if switch 8
> of block 1 is open (3.6MHz) or connected to Vcc via 10kOhm if switch 8
> of block 1 is closed (1.7MHz).
>
> That's too curious, so I'm probably wrong :-(
>
>
> BTW the capacitor between the processor and the EPROM is also used for
> timing purpose.
>
> - Ralf
>
>
I agree, that's curious.
Perhaps the long delay is the reset for the card.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351438 is a reply to message #351434] |
Sat, 26 August 2017 01:24 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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Michael J. Mahon <mjmahon@aol.com> wrote:
> Ralf Kiefer <R.Kiefer.SPAEM@gmx.de> wrote:
>> Michael J. Mahon wrote:
>>
>>> I suspect that the 10uF capacitor is a filter/bypass capacitor on the +5v,
>>> not a timing capacitor.
>>
>> Sorry, no. "-" of that capacitor is connected to GND, but "+" is
>> connected to Vcc via the resistor (150kOhm) and to pin 7 of the LS123.
>> You can recognize this connection on the component side.
>>
>> Pin 6 of the LS123 is connected to GND. This is the "traditional" usage
>> of the LS123 as described in the TI documentation mentioned before.
>>
>> There is just one question: is this the delay generation?
>>
>> It's a bit more complicated :-( The first half of the LS123 is used
>> also in this context. Pin 4 and pin 5 of the LS123 are connected to the
>> LS32, pin 1 and pin 2. The next question: the function of that first
>> half LS123. Pin 15 is connected to the capacitor nearby marked with
>> "330" (nF ?). This capacitor is connected to Vcc via 110kOhm if switch 8
>> of block 1 is open (3.6MHz) or connected to Vcc via 10kOhm if switch 8
>> of block 1 is closed (1.7MHz).
>>
>> That's too curious, so I'm probably wrong :-(
>>
>>
>> BTW the capacitor between the processor and the EPROM is also used for
>> timing purpose.
>>
>> - Ralf
>>
>>
>
> I agree, that's curious.
>
> Perhaps the long delay is the reset for the card.
>
BTW, capacitors under 1uF marked with three digits (nne) are usually nn x
10^e pF, which is much too small for the expected use. If it were 330nF
with 110k, the time constant would be a reasonable 36 milliseconds, but
that would be an unusual way to mark a 0.33uF capacitor.
Weird.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #351795 is a reply to message #351438] |
Fri, 01 September 2017 17:49 |
Steven Hirsch
Messages: 798
Registered: October 2012
Karma: 0
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Senior Member |
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On 08/26/2017 01:24 AM, Michael J. Mahon wrote:
>
> BTW, capacitors under 1uF marked with three digits (nne) are usually nn x
> 10^e pF, which is much too small for the expected use. If it were 330nF
> with 110k, the time constant would be a reasonable 36 milliseconds, but
> that would be an unusual way to mark a 0.33uF capacitor.
I may still have my notes somewhere. The information came from one of the
hardware designers at AE: Steven Malachek.
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| Re: Transwarp - How do they work? [message #354085 is a reply to message #347789] |
Mon, 09 October 2017 20:58 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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Somewhere I read that the DMA line is pulled up by a 3300 ohm resistor. I am putting together a proto-board that needs to pull this down at startup because my chip takes a few seconds to initialize. Normally I'd just pull this down with a 10k resistor but seeing that this already has a pull-up on it I don't know what the consequences would be (eg. will it act as a voltage divider?). Would anyone know what the best approach to this is?
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| Re: Transwarp - How do they work? [message #354096 is a reply to message #354085] |
Mon, 09 October 2017 21:51 |
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Originally posted by: James Davis
On Monday, October 9, 2017 at 5:58:45 PM UTC-7, Anthony Ortiz wrote:
> Somewhere I read that the DMA line is pulled up by a 3300 ohm resistor. I am putting together a proto-board that needs to pull this down at startup because my chip takes a few seconds to initialize. Normally I'd just pull this down with a 10k resistor but seeing that this already has a pull-up on it I don't know what the consequences would be (eg. will it act as a voltage divider?). Would anyone know what the best approach to this is?
Yes, I believe it would act as a voltage divider. You probably need a transistor circuit to pull it down. But, I am not an electronics engineer, just a retired electrician. MJM would know better.
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| Re: Transwarp - How do they work? [message #354100 is a reply to message #354096] |
Tue, 10 October 2017 01:11 |
Michael J. Mahon
Messages: 1767
Registered: October 2012
Karma: 0
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Senior Member |
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James Davis <JPD.Enterprises@outlook.com> wrote:
> On Monday, October 9, 2017 at 5:58:45 PM UTC-7, Anthony Ortiz wrote:
>> Somewhere I read that the DMA line is pulled up by a 3300 ohm resistor.
>> I am putting together a proto-board that needs to pull this down at
>> startup because my chip takes a few seconds to initialize. Normally I'd
>> just pull this down with a 10k resistor but seeing that this already has
>> a pull-up on it I don't know what the consequences would be (eg. will it
>> act as a voltage divider?). Would anyone know what the best approach to this is?
>
> Yes, I believe it would act as a voltage divider. You probably need a
> transistor circuit to pull it down. But, I am not an electronics
> engineer, just a retired electrician. MJM would know better.
>
James is correct, a 10k resistor won't pull the line to logic low.
You should use an open collector output to drive the line low, and you are
never permitted to drive it high--after all, anyone can pull it low (of
course, anyone pulling /DMA low should have permission).
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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| Re: Transwarp - How do they work? [message #354111 is a reply to message #354085] |
Tue, 10 October 2017 04:54 |
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Originally posted by: Jorge
On Tuesday, October 10, 2017 at 2:58:45 AM UTC+2, Anthony Ortiz wrote:
> needs to pull this down at startup because my chip takes a few seconds to initialize.
On a real Apple II you can't pull down DMA for so long, the 6502 is not static. In most of the (rubbish) IIs that came later, with 65c02s and beyond, yes you can.
--
Jorge.
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| Re: Transwarp - How do they work? [message #354112 is a reply to message #354109] |
Tue, 10 October 2017 04:58 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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Oh, and for the initial state during startup, should I pull input low (of the SN7407N) using a 10k resistor? I checked data sheet and logic table doesn't say what output would be if input is floating (as would be the case during startup).
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| Re: Transwarp - How do they work? [message #354116 is a reply to message #354111] |
Tue, 10 October 2017 06:56 |
anthonypaulo
Messages: 531
Registered: September 2013
Karma: 0
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Senior Member |
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You should be able to hold DMA for as long as you want, otherwise how do accelerators such as the Transwarp work? I realize that the 6502 will lose all state but that's fine with me, whenever I want to relinquish control I'll release the DMA line and restart the computer.
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